Memory controller implemented error correction code memory
Devices and techniques for memory controller implemented error correction code (ECC) memory are disclosed herein. ECC groups may be placed across banks of the memory. In some examples, an ECC group is a collection of bytes equal to one row in one bank. Also, the placement may restrict a given bank to a single member of the ECC group. A memory operation can be received and executed using the ECC groups.
1. A memory device for error correction code (ECC) memory, the memory device comprising:
a memory array; and
a memory controller to:
designate ECC groups across banks of the memory array, any given ECC group being a collection of bytes equal to one row in one bank, wherein the ECC groups designation restricts a given bank to a single member of the ECC groups, wherein, to designate the ECC groups, the memory controller starts at a first row offset within a first bank and increments the first row offset with each successive bank after the first bank, wherein an increment is subject to a modulus operation for all banks in the memory array;
receive a memory operation; and
execute the memory operation using the ECC groups.
2. The memory device of claim 1 , wherein the memory device comprises a dynamic random access (DRAM) memory.
3. The memory device of claim 2 , wherein the banks reside on:
a single DRAM integrated circuit (IC) of the memory array; or
several DRAM integrated circuits (ICs) on a dual in-line memory module (DIMM) of the memory array.
4. The memory device of claim 1 , wherein an ECC group is one-eighth of a row width.
5. The memory device of claim 1 , wherein the increments are implemented by an exclusive-OR of:
three most significant bits of an address for the memory array; with
three least significant row bits of the address.
6. The memory device of claim 1 , wherein one ECC group of the ECC groups is unused.
7. The memory device of claim 6 , wherein the one ECC group that is unused is determined by a replacement of three most significant bits of an address for the memory array with three least significant bank bits of the address.
8. The memory device of claim 1 , wherein the memory controller is to designate a set of data groups across the banks, wherein the designation of the set of data groups restricts the given bank to a single data group from a member of the set of data groups.
9. The memory device of claim 8 , wherein, to execute the memory operation using the ECC groups, the memory controller is to:
retrieve an ECC group, from the ECC groups, that is at a same row offset as a data group subject to the memory operation; and
perform an ECC operation using the retrieved ECC group that is at the same row offset as the data group.
10. The memory device of claim 1 , wherein the memory array includes several memory integrated circuits (ICs) and none of the several memory ICs are exclusively ECC.
11. A method for memory controller implemented error correction code (ECC) memory, the method comprising:
designating ECC groups across banks of a memory array, any given ECC group being a collection of bytes equal to one row in one bank, wherein the ECC groups designation restricts a given bank to a single member of the ECC groups, wherein, designating the ECC groups starts at a first row offset within a first bank and increments the first row offset with each successive bank after the first bank, wherein an increment is subject to a modulus operation for all banks in the memory array;
receiving a memory operation; and
executing the memory operation using the ECC groups.
12. The method of claim 11 , wherein the memory operation comprises a dynamic random access (DRAM) memory access.
13. The method of claim 12 , wherein the banks reside on:
a single DRAM integrated circuit (IC) of the memory array; or
several DRAM integrated circuits (ICs) on a dual in-line memory module (DIMM) of the memory array.
14. The method of claim 11 , wherein an ECC group is one-eighth of a row width.
15. The method of claim 11 , wherein the increments are implemented by exclusive-ORing:
three most significant bits of an address for the memory array; with
three least significant row bits of the address.
16. The method of claim 11 , wherein one ECC group of the ECC groups is unused.
17. The method of claim 16 , wherein the one ECC group that is unused is determined by using three most significant bits of an address for the memory array as three least significant bank bits of the address.
18. The method of claim 11 , comprising designating a set of data groups across the banks, wherein designating the set of data groups restricts the given bank to a single data group from a member of the set of data groups.
19. The method of claim 18 , wherein executing the memory operation using the ECC groups includes:
retrieving an ECC group, from the ECC groups, that is at a same row offset as a data group subject to the memory operation; and
performing an ECC operation using the retrieved ECC group that is at the same row offset as the data group.
20. The method of claim 11 , wherein the memory array includes several memory integrated circuits (ICs) and none of the several memory ICs are exclusively ECC.
21. A non-transitory machine readable medium including instructions for memory controller implemented error correction code (ECC) memory, the instructions, when executed by a machine, cause the machine to perform operations comprising:
designating ECC groups across banks of a memory array, any given ECC group being a collection of bytes equal to one row in one bank, wherein the ECC groups designation restricts a given bank to a single member of the ECC groups, wherein, designating the ECC groups starts at a first row offset within a first bank and increments the first row offset with each successive bank after the first bank, wherein an increment is subject to a modulus operation for all banks in the memory array;
receiving a memory operation; and
executing the memory operation using the ECC groups.
22. The non-transitory machine readable medium of claim 21 , wherein the memory operation comprises a dynamic random access (DRAM) memory access.
23. The non-transitory machine readable medium of claim 22 , wherein the banks reside on:
a single DRAM integrated circuit (IC) of the memory array; or several DRAM integrated circuits (ICs) on a dual in-line memory module (DIMM) of the memory array.
24. The non-transitory machine readable medium of claim 21 , wherein an ECC group is one-eighth of a row width.
25. The non-transitory machine readable medium of claim 21 , wherein the increments are implemented by exclusive-ORing:
three most significant bits of an address for the memory array; with three least significant row bits of the address.
26. The non-transitory machine readable medium of claim 21 , wherein one ECC group of the ECC groups is unused.
27. The non-transitory machine readable medium of claim 26 , wherein the one ECC group that is unused is determined by using three most significant bits of an address for the memory array as three least significant bank bits of the address.
28. The non-transitory machine readable medium of claim 21 , wherein the operations comprise designating a set of data groups across the banks, wherein designating the set of data groups restricts the given bank to a single data group from a member of the set of data groups.
29. The non-transitory machine readable medium of claim 28 , wherein executing the memory operation using the ECC groups includes:
retrieving an ECC group, from the ECC groups, that is at a same row offset as a data group subject to the memory operation; and
performing an ECC operation using the retrieved ECC group that is at the same row offset as the data group.
30. The non-transitory machine readable medium of claim 21 , wherein the memory array includes several memory integrated circuits (ICs) and none of the several memory ICs are exclusively ECC.