Patent Assignment
Reel/Frame 045267/0833
Supplement No. 7 to Patent Security Agreement
Recorded: 2018-02-06
Pages: 29
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2018-01-23
Assignee
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(396)
Apparatuses and Methods for an Operating System Cache in a Solid State Device
PCT:
PCT/US2017/055845 ↗
Semiconductor Devices and Methods of Fabrication
PCT:
PCT/US2017/056956 ↗
Integrated Memory Assemblies Comprising Multiple Memory Array Decks
PCT:
PCT/US2017/059022 ↗
Cell Disturb Prevention Using a Leaker Device
PCT:
PCT/US2017/059319 ↗
Apparatuses and Methods for Memory Alignment
PCT:
PCT/US2017/059659 ↗
A Construction of Integrated Circuitray and a Method of Forming an Elevationally-Extending Conductor Laterally Between a Pair of Structures
PCT:
PCT/US2017/059992 ↗
Semiconductor Die Assembly Having Heat Spreader That Extends Through Underlying Interposer and Related Technology
PCT:
PCT/US2017/062621 ↗
Memory Protocol
PCT:
PCT/US2017/063581 ↗
Apparatuses and Methods for Calibrating Adjustable Impedances of a Semiconductor Device
PCT:
PCT/US2017/065391 ↗
Board Edge Connector
PCT:
PCT/US2017/065513 ↗
Integrated Memory, Integrated Assemblies, and Methods of Forming Memory Arrays
PCT:
PCT/US2017/065993 ↗
Apparatuses and Methods for a Memory Device with Dual Common Data I/O Lines
PCT:
PCT/US2017/066769 ↗
Methods of Forming an Array of Capacitors, Methods of Forming an Array of Memory Cells Individually Comprising a Capacitor and a Transistor, Arrays of Capacitors, and Arrays of Memory Cells Individually Comprising a Capacitor and a Transistor
PCT:
PCT/US2017/068197 ↗
Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors
PCT:
PCT/US2017/068219 ↗
Arrays of Memory Cells Individually Comprising a Capacitor and an Elevationally-Extending Transistor, Methods of Morming a Tier of an Array of Memory Cells, and Methods of Forming an Array of Memory Cells Individually Comprising a Capacitor and an Elevationally-Extending Transistor
PCT:
PCT/US2017/068223 ↗
Memory Cells, Arrays of Two Transistor-One Capacitor Memory Cells, Methods of Forming an Array of Two Transistor-One Capacitor Memory Cells, and Methods Used in Fabricating Integrated Circuitry
PCT:
PCT/US2017/068227 ↗
Memory Cells and Methods of Forming a Capacitor
PCT:
PCT/US2017/068317 ↗
A Memory Cell, an Array of Memory Cells Individually Comprising a Capacitor and a Transistor with the Array Comprising Rows of Access Lines and Columns of Digit Lines, a 2T-1C Memory Cell, and Methods of Forming an Array of Capacitors and Access Transistors There-Above
PCT:
PCT/US2017/068425 ↗
Memory Cells, Integrated Structures and Memory Arrays
PCT:
PCT/US2017/069113 ↗
Directed Sanitization of Memory
PCT:
PCT/US2018/013048 ↗
Apparatuses and Methods for Providing Internal Clock Signals of Different Clock Frequencies in a Memory Device
PCT:
PCT/US2018/013073 ↗
Memory Protocol with Command Priority
PCT:
PCT/US2018/014345 ↗
Method for Manufacturing a Wafer Level Package
Application:
14/835,687 →
Publication:
US 2017/0062240
Advanced Memory Interfaces and Methods
Semiconductor Package with Embedded Mim Capacitor, and Method of Fabricating Thereof
Mim Capacitor with Enhanced Capacitance
Application:
15/396,828 →
Publication:
US 2018/0190761
Semiconductor Package and Method for Fabricating the Same
Methods of Programming Different Portions of Memory Cells of a String of Series-Connected Memory Cells
Systems and Methods to Selectively Connect Antennas to Receive and Backscatter Radio Frequency Signals
Microprocessor Architecture Having Alternative Memory Access Paths
Software Distribution Method and Apparatus
Application:
15/670,961 →
Publication:
US 2018/0025134
Memory Decision Feedback Equalizer Testing
Apparatuses and Methods Involving Accessing Distributed Sub-Blocks of Memory Cells
Analog Assisted Digital Switch Regulator
Methods and Apparatus for Providing Redundancy in Memory
Sequential Memory Access Operations
Memory Devices for Reading Memory Cells of Different Memory Planes
Three Dimensional Memory and Methods of Forming the Same
Autonomous Memory Architecture
Systems and Methods for Threshold Voltage Modification and Detection
Patent:
10,127,994 →
Application:
15/789,167 →
Virtual Partition Management in a Memory Device
Host Accelerated Operations in Managed Nand Devices
Namespaces Allocation in Non-Volatile Memory Devices
On-Die Termination Architecture
Namespace Size Adjustment in Non-Volatile Memory Devices
Namespace Management in Non-Volatile Memory Devices
Memory Sense Amplifiers and Memory Verification Methods
Command Selection Policy
Devices and Methods to Write Background Data Patterns in Memory Devices
Memory Cell with Independently-Sized Electrode
Systems, Devices, and Methods for Selective Communication Through an Electrical Connector
Apparatuses Including Multiple Read Modes and Methods for Same
Oxide Based Memory
Assemblies Including Heat Dispersing Elements and Related Systems and Methods
Connection Verification Technique
Apparatus and Methods for Refreshing Memory
Patent:
10,170,174 →
Application:
15/796,340 →
Memory Cells and Memory Arrays
Backside Stealth Dicing Through Tape Followed by Front Side Laser Ablation Dicing Process
Patent:
10,079,169 →
Application:
15/797,029 →
Integrated Memory Assemblies Comprising Multiple Memory Array Decks
3DI Solder Cup
Apparatuses and Methods to Selectively Perform Logical Operations
Dynamic L2P Cache
Method for 3D Ink Jet TCB Interconnect Control
Memory Devices with Multiple Sets of Latencies and Methods for Operating the Same
Methods of Forming Nanostructures Using Self-Assembled Nucleic Acids, and Nanostructures Thereof
Common Pool Management
End of Life Performance Throttling to Prevent Data Loss
Block Read Count Voltage Adjustment
Slc Page Read
Systems and Methods for Maintaining Refresh Operations of Memory Banks Using a Shared Address Path
Patent:
10,141,041 →
Application:
15/800,267 →
Nand Flash Thermal Alerting
Uninterrupted Read of Consecutive Pages for Memory
Peripheral Logic Circuits Under Dram Memory Arrays
Selectable Trim Settings on a Memory Device
Configurable Trim Settings on a Memory Device
Trim Setting Determination for a Memory Device
Trim Setting Determination on a Memory Device
Semiconductor Device
Anti-Eclipse Circuitry with Tracking of Floating Diffusion Reset Level
Memory Arrays
Patent:
10,083,734 →
Application:
15/804,981 →
Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor
Apparatuses and Methods for Compute Components Formed Over an Array of Memory Cells
Multiple Data Channel Memory Module Architecture
Semiconductor Device Assemblies Including Multiple Shingled Stacks of Semiconductor Dies
Tracking and Correction of Timing Signals
Ufs Based Idle Time Garbage Collection Management
Patent:
10,521,146 →
Application:
15/808,567 →
Transistors and Memory Arrays
Apparatuses and Methods for Repairing Memory Devices Including a Plurality of Memory Die and an Interface
Memory Arrays Comprising Ferroelectric Capacitors
Invert Operations Using Sensing Circuitry
Computing Reduction and Prefix Sum Operations in Memory
CAPACITOR HAVING BOTTOM ELECTRODE COMPRISING TiN
Semiconductor Devices with Package-Level Configurability
Patent:
10,128,229 →
Application:
15/811,572 →
Semiconductor Devices with Post-Probe Configurability
Patent:
10,283,462 →
Application:
15/811,579 →
Cell Contact
Memory Wear Leveling
Application:
15/812,932 →
Publication:
US 2018/0067661
Systems and Methods for Performing a Write Pattern in Memory Devices
Namespace Change Propagation in Non-Volatile Memory Devices
Patent:
10,223,254 →
Application:
15/814,634 →
Namespace Encryption in Non-Volatile Memory Devices
Namespace Mapping Optimization in Non-Volatile Memory Devices
Electronic Device with a Fuse Read Mechanism
Patent:
10,115,474 →
Application:
15/814,835 →
Capacitors and Integrated Assemblies Which Include Capacitors
Namespace Mapping Structual Adjustment in Non-Volatile Memory Devices
Apparatuses and Methods for Mixed Charge Pumps with Voltage Regulator Circuits
Providing Energy Information to Memory
Reclaimable Semiconductor Device Package and Associated Systems and Methods
Memory Devices with Distributed Block Select for a Vertical String Driver Tile Architecture
Semiconductor Device Including Fuse Circuit
Semiconductor Device with a Multi-Layered Encapsulant and Associated Systems, Devices, and Methods
Integrated Assemblies and Methods of Forming Integrated Assemblies
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
Data Categorization Based on Invalidation Velocities
Last Written Page Searching
Pulsed Integrator and Memory Techniques
Comparison Operations in Memory
Data Shifting
Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems
Power Reduction Technique During Write Bursts
Patent:
10,255,967 →
Application:
15/824,535 →
Systems and Methods for Temperature Sensor Access in Die Stacks
Systems and Methods for Improving Write Preambles in Ddr Memory Devices
Signal Training for Prevention of Metastability Due to Clocking Indeterminacy
Comparing Input Data to Stored Data
Methods of Forming an Array of Cross Point Memory Cells
Operations on Memory Cells
Wireless Devices and Systems Including Examples of Configuration During an Active Time Period
Apparatuses and Methods for Current Limitation in Threshold Switching Memories
Semiconductor Device Packages and Related Methods
Semiconductor Devices, Memory Dies and Related Methods
Semiconductor Devices with Duplicated Die Bond Pads and Associated Device Packages and Methods of Manufacture
Wear Leveling in Solid State Drives
Electronic Device with a Fuse-Read Trigger Mechanism
Tcb Bond Tip Design to Mitigate Top Die Warpage and Solder Stretching Issue
Semiconductor Device Assembly with Pillar Array
Reprogrammable Non-Volatile Ferroelectric Latch for Use with a Memory Controller
Memory Systems and Memory Programming Methods
Data Movement Operations in Non-Volatile Memory
Two-Part Programming Methods
Input Buffer Circuit
Patent:
10,211,832 →
Application:
15/832,431 →
Selectors on Interface Die for Memory Device
Apparatuses and Methods for Providing Bias Signals According to Operation Modes as Supply Voltages Vary in a Semiconductor Device
Apparatuses and Methods for Providing Bias Signals in a Semiconductor Device
Patent:
10,199,081 →
Application:
15/833,688 →
Systems and Methods for Plate Voltage Regulation During Memory Array Access
Wave Pipeline
Skew Reduction of a Wave Pipeline in a Memory Device
Apparatuses and Methods for Calibrating Adjustable Impedances of a Semiconductor Device
Semiconductor Memory Device and Erase Method Including Changing Erase Pulse Magnitude for a Memory Array
Apparatuses Having an Interconnect Extending from an Upper Conductive Structure, Through a Hole in Another Conductive Structure, and to an Underlying Structure
Apparatuses and Methods for Concentrated Arrangement of Transistors of Multiple Amplifier Circuits
Resistive Memory Cell Structures and Methods
Read Threshold Voltage Selection
Systems and Methods for Writing Zeros to a Memory Array
Systems and Methods for Writing Zeros to a Memory Array
Semiconductor Device Including a Clock Adjustment Circuit
Apparatuses and Methods for Indicating an Operation Type Associated with a Power Management Event
Ferroelectric Memory Cell Recovery
Apparatuses and Methods for Removing Defective Energy Storage Cells from an Energy Storage Array
Apparatuses and Methods for Data Transmission Offset Values in Burst Transmissions
Inductive Testing Probe Apparatus for Testing Semiconductor Die and Related Systems and Methods
Error Correction Code Scrub Scheme
Ferroelectric Capacitor, Ferroelectric Field Effect Transistor, And Method Used In Forming An Electronic Component Comprising Conductive Material And Ferroelectric Material
Apparatuses and Methods for Comparing a Current Representative of a Number of Failing Memory Cells
Power Interrupt Management
Performance Level Adjustments in Memory Devices Based on Workload Estimation
Application:
15/840,709 →
Publication:
US 2019/0179547
Methods for Fabricating a Semiconductor Memory Device
Apparatuses and Methods for Transistor Protection by Charge Sharing
Apparatuses Including Memory Cells and Methods of Operation of Same
APPARATUSES AND METHODS FOR CONFIGURING I/Os OF MEMORY FOR HYBRID MEMORY MODULES
Method and Apparatus for Decoding Command Operations for a Semiconductor Device
Decision Feedback Equalizer
Patent:
10,291,439 →
Application:
15/841,144 →
Test Mode Circuit for Memory Apparatus
Textured Memory Cell Structures
Multilevel Addressing
Memory Having a Static Cache and a Dynamic Cache
Methods of Fabricating Conductive Traces and Resulting Structures
Semiconductor Devices Including Conductive Lines and Methods of Forming the Semiconductor Devices
Multi-Level Self-Selecting Memory Device
Techniques to Access a Self-Selecting Memory Device
Apparatuses and Methods for Subarray Addressing
Providing Power Availability Information to Memory
Methods of Incorporating Leaker Devices into Capacitor Configurations to Reduce Cell Disturb
Ferroelectric Assemblies
Methods Of Forming A Transistor And Methods Of Forming An Array Of Memory Cells
Integrated Assemblies Having Anchoring Structures Proximate Stacked Memory Cells
Techniques for Accessing an Array of Memory Cells to Reduce Parasitic Coupling
Multi-Phase Clock Division
Single Plate Configuration and Memory Array Operation
Constructions Comprising Stacked Memory Arrays
Charge Separation for Memory Sensing
Apparatuses and Methods for Subrow Addressing
Current Separation for Memory Sensing
Providing Autonomous Vehicle Assistance
Secure Message Including a Vehicle Private Key
Vehicle Secure Messages Based on a Vehicle Private Key
Implementing Safety Measures in Applications
Secure Vehicle Control Unit Update
Apparatuses and Methods for Forming Die Stacks
Using Sacrificial Solids in Semiconductor Processing
Apparatuses and Methods for Charging a Global Access Line Prior to Accessing a Memory
Hydrosilylation in Semiconductor Processing
Charge Mirror-Based Sensing for Ferroelectric Memory
Gas Residue Removal
Removing a Sacrificial Material via Sublimation in Forming a Semiconductor
Solder Bond Site Including an Opening with Discontinuous Profile
Freezing a Sacrificial Material in Forming a Semiconductor
Assemblies Having Vertically-Stacked Conductive Structures
Patent:
10,170,493 →
Application:
15/848,398 →
Semiconductor Devices Including Silver Conductive Materials
Apparatuses Including Electrodes Having a Conductive Barrier Material and Methods of Forming Same
Methods of Filling Horizontally-Extending Openings of Integrated Assemblies
Patent:
10,283,524 →
Application:
15/848,612 →
Control of Display Device for Autonomous Vehicle
Internal Clock Distortion Calibration Using Dc Component Offset of Clock Signal
Patent:
10,270,429 →
Application:
15/848,796 →
Transistors Comprising At Least One Of GaP, GaN, and GaAs
Utilizing Write Stream Attributes in Storage Write Commands
Electronic Device with an Output Voltage Booster Mechanism
Patent:
10,211,724 →
Application:
15/849,052 →
Electronic Device with a Charge Recycling Mechanism
Electronic Device with a Charging Mechanism
Non-Contact Measurement of Memory Cell Threshold Voltage
Searching Data in Parallel Using Processor-in-Memory Devices
Array Of Cross Point Memory Cells
Nvdimm with Removable Storage
Multi-Decks Memory Device Including Inter-Deck Switches
Management of Strobe/Clock Phase Tolerances During Extended Write Preambles
Voltage Reference Computations for Memory Decision Feedback Equalizers
Dual Resistive-Material Regions for Phase Change Memory Devices
Array Of Cross Point Memory Cells And Methods Of Forming An Array Of Cross Point Memory Cells
Apparatuses and Methods for Providing Frequency Divided Clocks
Patent:
10,141,942 →
Application:
15/851,126 →
Systems and Methods for Improving Fuse Systems in Memory Devices
Methods of Processing Semiconductor Device Structures and Related Systems
Methods for Processing Semiconductor Dice and Fabricating Assemblies Incorporating Same
Patent:
10,163,693 →
Application:
15/851,304 →
Providing Autonomous Vehicle Maintenance
Double Patterning Method to Form Sub-Lithographic Pillars
Application:
15/851,422 →
Publication:
US 2018/0114813
Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Methods Of Processing Silicon Nitride-Comprising Materials
Programmatically Identifying a Personality of an Autonomous Vehicle
Arrays Of Memory Cells And Methods Of Forming An Array Of Memory Cells
Semiconductor Devices Having Electrically and Optically Conductive Vias, and Associated Systems and Methods
Patent:
10,141,259 →
Application:
15/852,339 →
Memory Cells, Arrays Of Two Transistor-One Capacitor Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry
Conductive Structures and Assemblies Having Vertically-Stacked Memory Cells Over Conductive Structures
Assemblies Having Vertically-Extending Structures
Auto-Referenced Memory Cell Read Techniques
Auto-Referenced Memory Cell Read Techniques
Systems, Methods and Devices for Programming a Multilevel Resistive Memory Cell
Physical Unclonable Function Using Message Authentication Code
Interconnect Structures for Preventing Solder Bridging, and Associated Systems and Methods
Patent:
10,297,561 →
Application:
15/853,512 →
Apparatuses and Methods for Duty Cycle Error Correction of Clock Signals
Adjustable Delay Circuit for Optimizing Timing Margin
Material Implication Operations in Memory
Memory Cells and Semiconductor Devices Including Ferroelectric Materials
Half Density Ferroelectric Memory and Operation
Memory Arrays and Methods of Forming Memory Arrays
Apparatus and Methods for via Connection with Reduced via Currents
Multi-Level Signaling in Memory with Wide System Interface
Apparatuses and Methods for Concurrently Accessing Multiple Memory Planes of a Memory During a Memory Access Operation
Three-Dimensional Memory Apparatuses and Methods of Use
Methods of Programming Memories Having a Shared Resistance Variable Material
Systems Having a Resistive Memory Device
Memory Cells and Memory Arrays
Techniques for Sensing Logic Values Stored in Memory Cells Using Sense Amplifiers That Are Selectively Isolated from Digit Lines
Determination of Reliability of Vehicle Control Commands via Memory Test
Ground Reference Scheme for a Memory Cell
Determination of Reliability of Vehicle Control Commands via Redundancy
Memory Device Write Circuitry
Patent:
10,181,344 →
Application:
15/855,485 →
Systems and Methods for Performing Row Hammer Refresh Operations in Redundant Memory
Temporary Carrier Debond Initiation, and Associated Systems and Methods
Parallel Access Techniques Within Memory Sections Through Section Independence
Data Transfer Techniques for Multiple Devices on a Shared Bus
Conductive Hard Mask for Memory Device Formation
Methods Used In Forming At Least A Portion Of At Least One Conductive Capacitor Electrode Of A Capacitor That Comprises A Pair Of Conductive Capacitor Electrodes Having A Capacitor Insulator There-Between And Methods Of Forming A Capacitor
Thermal Insulation for Three-Dimensional Memory Arrays
Thermal Insulation for Three-Dimensional Memory Arrays
Apparatuses and Methods for Sensing a Phase-Change Test Cell and Determining Changes to the Test Cell Resistance Due to Thermal Exposure
Apparatuses and Methods for Sensing a Phase-Change Test Cell and Determining Changes to the Test Cell Resistance Due to Thermal Exposure
Determination of Reliability of Vehicle Control Commands using a Voting Mechanism
Apparatuses and Methods for Power Efficient Driver Circuits
Three-Dimensional Memory Apparatus and Method of Manufacturing the Same
Charge Loss Failure Mitigation
Patent:
10,242,747 →
Application:
15/856,132 →
Apparatus and Method for Instant-on Quadra-Phase Signal Generator
Components and Systems for Cleaning a Tool for Forming a Semiconductor Device, and Related Methods
Security of User Data Stored in Shared Vehicles
Power Reduction Technique During Read/Write Bursts
Patent:
10,157,659 →
Application:
15/856,826 →
Memory Controller Implemented Error Correction Code Memory
Techniques to Update a Trim Parameter in Non-Volatile Memory
Techniques for Precharging a Memory Cell
Drift Mitigation with Embedded Refresh
Patent:
10,269,442 →
Application:
15/857,125 →
Apparatuses for Reducing Off State Leakage Currents
Jitter Cancellation with Automatic Performance Adjustment
Patent:
10,164,618 →
Application:
15/857,157 →
Polarity-Conditioned Memory Cell Write Operations
Methods of Forming Semiconductor Structures Having Stair Step Structures
Patent:
10,269,625 →
Application:
15/857,197 →
Apparatuses and Methods for Sense Line Architectures for Semiconductor Memories
Resistive Random Access Memory Having Multi-Cell Memory Bits
Methods of Storing and Retrieving Information for Rram with Multi-Cell Memory Bits
Semiconductor Constructions
Apparatuses and Methods for Providing Data to a Configurable Storage Area
Memory Arrays and Methods of Forming Memory Cells
Methods and Apparatuses for Command Shifter Reduction
Temperature-Based Memory Operations
Semiconductor Device and Error Correction Method
Semiconductor Structures Including Multi-Portion Liners
Methods of Forming Semiconductor Devices Comprising Silicon Nitride on High Aspect Ratio Features
Methods of Forming Integrated Assemblies
Methods of Forming High Aspect Ratio Openings and Methods of Forming High Aspect Ratio Features
Methods of Forming Staircase Structures
Patent:
10,147,638 →
Application:
15/858,072 →
Semiconductor Devices Including Control Logic Structures, Electronic Systems, and Related Methods
Distributed Architecture for Enhancing Artificial Neural Network
Application:
15/858,143 →
Publication:
US 2019/0205744
Semiconductor Devices, and Related Control Logic Assemblies, Control Logic Devices, Electronic Systems, and Methods
Patent:
10,297,290 →
Application:
15/858,188 →
Memory Cells, Memory Systems, and Memory Programming Methods
Semiconductor Devices Including Control Logic Levels, and Related Memory Devices, Control Logic Assemblies, Electronic Systems, and Methods
Construction Of Integrated Circuitry And A DRAM Construction
Managing Partial Superblocks in a Nand Device
Pillar-Last Methods for Forming Semiconductor Devices
Self-Learning in Distributed Architecture for Enhancing Artificial Neural Network
Multi-Gate String Drivers Having Shared Pillar Structure
Semiconductor Device Assemblies Including Multiple Stacks of Different Semiconductor Dies
Clamp Elements for Phase Change Memory Arrays
Cell-Based Reference Voltage Generation
Methods, Apparatuses, and Circuits for Programming a Memory Device
Method, System, and Device for L-Shaped Memory Component
Accessing Memory Cells in Parallel in a Cross-Point Array
Cross-Point Memory and Methods for Fabrication of Same
Dynamic Adjustment of Memory Cell Digit Line Capacitance
Writing to Cross-Point Non-Volatile Memory
Multi-Level Storage in Ferroelectric Memory
Apparatuses for Modulating Threshold Voltages of Memory Cells
Apparatuses and Methods for Photonic Communication and Photonic Addressing
Transistors, Memory Cells and Semiconductor Constructions Comprising Ferroelectric Gate Dielectric
Methods Comprising an Atomic Layer Deposition Sequence
Memory Cells
Method, Apparatus and System Providing a Storage Gate Pixel with High Dynamic Range
Method for Stress Reduction in Semiconductor Package via Carrier
Systems and Methods for Providing File Information in a Memory System Protocol
I/O Buffer Offset Mitigation
Memory Decision Feedback Equalizer Bias Level Generation
Memory and Electronic Devices with Reduced Operational Energy in Chalcogenide Material
Semiconductor Devices Including Stair-Step Structures
Controlling Discharge of a Control Gate Voltage
Stair Step Formation Using at Least Two Masks
Method for Mount Tape Die Release System for Thin Die Ejection
Patent:
10,043,688 →
Application:
15/867,071 →
Transistors Having Dielectric Material Containing Non-Hydrogenous Ions and Methods of Their Fabrication
Removal of Metal
Apparatuses and Methods for Maintaining a Duty Cycle Error Counter
Power Management
Access Line Management in a Memory Device
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
Patent:
10,297,307 →
Application:
15/870,657 →
Voltage Correction Computations for Memory Decision Feedback Equalizers
Patent:
10,277,427 →
Application:
15/871,636 →
Methods and Systems for Data Analysis in a State Machine
Computerized Apparatus with a High Speed Data Bus
Compensating for Memory Input Capacitance
Patent:
10,229,890 →
Application:
15/872,456 →
Uniform Electrochemical Plating of Metal Onto Arrays of Pillars Having Different Lateral Densities and Related Technology
Monitoring Error Correction Operations Performed in Memory
Methods of Forming Resistive Memory Elements
Data Storage Management
Data Transfer in Sensing Components
Semiconductor Device Packages with Direct Electrical Connections and Related Methods
Determining Soft Data for Fractional Digit Memory Cells
Methods of Forming Semiconductor Device Structures Including Staircase Structures
Performance Allocation among Users for Accessing Non-volatile Memory Devices
Apparatuses and Methods for Refreshing Memory of a Semiconductor Device
Management of Storage Resources Allocated from Non-volatile Memory Devices to Users
Methods of Patterning a Target Layer
Solid State Storage Device with Command and Control Access
Apparatuses and Methods for Calculating Row Hammer Refresh Addresses in a Semiconductor Device
Enhanced Error Correcting Code Capability Using Variable Logical to Physical Associations of a Data Block
Semiconductor Devices with Seed and Magnetic Regions and Methods of Fabrication
Interconnections for 3D Memory
Identifying a Read Operation for a Storage Device Based on a Workload of a Host System
Application:
15/878,315 →
Publication:
US 2019/0227743
Variable Modulation Scheme
Application:
62/567,011 →
Multiplexing Distinct Signals on a Single Pin
Application:
62/567,016 →
Multiple Concurrent Modulation Schemes in a Memory System
Application:
62/567,018 →
Simplified Package Including Stacked Dies
Application:
62/567,021 →
Memory System That Supports Dual-Mode Modulation
Application:
62/567,028 →
Reconfigurable Memory Architectures
Application:
62/576,520 →
Frame Protocol of Memory Device
Application:
62/576,530 →
Apparatuses and Methods for Identifying Memory Devices of a Semiconductor Device Sharing an External Resistance
Application:
62/578,847 →
System Having a Hybrid Threading Processor, a Hybrid Threading Fabric Having Configurable Computing Elements, and a Hybrid Interconnection Network
Application:
62/579,749 →
Memory Devices and Systems with Parallel Impedance Adjustment Circuitry and Methods for Operating the Same
Application:
62/583,608 →
Multi-Port Storage-Class Memory Interface
Application:
62/587,026 →
Methods for on-Die Memory Termination and Memory Devices and Systems Employing the Same
Application:
62/590,096 →
Methods for on-Die Memory Termination and Memory Devices and Systems Employing the Same
Application:
62/590,116 →
System, Apparatus, and Related Method for Generating a Geospatial Interactive Composite Web-Based Image Map
Application:
62/591,352 →
Apparatuses and Methods Including Memory Commands for Semiconductor Memories
Application:
62/592,208 →
Diagonal Block Mapping
Application:
62/593,758 →
Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices
Application:
62/595,912 →
Translation System for Finer Grain Memory Architectures
Application:
62/597,304 →
Assemblies Having Conductive Structures Along Pillars of Semiconductor Material, and Methods of Forming Integrated Circuitry
Application:
62/609,875 →
Assemblies Comprising Memory Cells and Select Gates; and Methods of Forming Assemblies
Application:
62/609,884 →
Memory Arrays, and Methods of Forming Memory Arrays
Application:
62/610,640 →
Memory Arrays, and Methods of Forming Memory Arrays
Application:
62/610,657 →
Programmable Charge Storage Transistor, An Array Of Elevationally Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally Extending Strings of Memory Cells
Application:
62/610,846 →
Transistors And Arrays Of Elevationally-Extending Strings Of Memory Cells
Application:
62/610,847 →
Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array
Application:
62/610,851 →
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells
Application:
62/610,854 →
Controlling Discharge of a Control Gate Voltage
Application:
62/610,972 →
Methods Of Forming An Array Of Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge-Storage Transistor
Application:
62/611,136 →
Recessed Access Devices And DRAM Constructions
Application:
62/611,336 →
Methods of Forming Integrated Circuit Well Structures
Application:
62/611,694 →
Circuit-Protection Devices
Application:
62/611,874 →
Methods for Independent Memory Bank Maintenance and Memory Devices and Systems Employing the Same
Application:
62/612,004 →
Related Assignments
(18)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Aug 25, 2015
From: WU, TIEH-CHIANG; SHIH, SHING-YIH
To: INOTERA MEMORIES, INC.
Reel/Frame 036419/0255 →
Assignment of Assignor's Interest
Jan 3, 2017
From: CHIANG, HSU; SHIH, NENG-TAI; WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 040817/0646 →
Assignment of Assignor's Interest
Jan 3, 2017
From: SHIH, SHING-YIH; KUAN, SHIH-FAN; WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 040833/0020 →
Assignment of Assignor's Interest
Feb 9, 2017
From: SHIH, SHING-YIH
To: INOTERA MEMORIES, INC.
Reel/Frame 041208/0288 →
Assignment of Assignor's Interest
Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
Assignment of Assignor's Interest
May 3, 2017
From: TUTTLE, JOHN R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042225/0143 →
Assignment of Assignor's Interest
Aug 24, 2017
From: BREWER, TONY; WALLACH, STEVEN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043385/0398 →
Assignment of Assignor's Interest
Sep 26, 2017
From: SREERAMANENI, RAGHUKIRAN; TAYLOR, JENNIFER E.; LIU, LIANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043691/0318 →
Change of Name
Oct 24, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY TAIWAN, INC.
Reel/Frame 044786/0588 →
Change of Name
Oct 24, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY TAIWAN, INC.
Reel/Frame 044802/0082 →
Change of Name
Oct 24, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY TAIWAN, INC.
Reel/Frame 044283/0711 →
Assignment of Assignor's Interest
Oct 27, 2017
From: LIANG, KE; XU, JUN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 043966/0264 →
Assignment of Assignor's Interest
Jan 30, 2018
From: MICRON TECHNOLOGY TAIWAN, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044777/0233 →
Assignment of Assignor's Interest
Feb 1, 2018
From: MICRON TECHNOLOGY TAIWAN, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044801/0990 →
Assignment of Assignor's Interest
Feb 2, 2018
From: MICRON TECHNOLOGY TAIWAN, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044822/0445 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →