IP Library Granted Patent US 10,163,506
Granted Patent B2
US 10,163,506 · App. 15/841,118 · Granted Dec 25, 2018

Apparatuses including memory cells and methods of operation of same

Inventors: Agostino Pirovano (Milan, IT); Innocenzo Tortorelli (Cernusco sul Naviglio, IT); Andrea Redaelli (Castatenovo, IT); Fabio Pellizzer (Boise, ID)
Assignee: Micron Technology, Inc.
G11C13/0069G11C13/0004G11C13/004G11C13/0026G11C13/0028G11C13/0097
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Quick Facts
Patent No.
US 10,163,506
App. No.
15/841,118
Granted
Dec 25, 2018
Kind
B2
Abstract

Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

Claims (32)

1. An apparatus, comprising:

a memory cell comprising:

a memory element; and

a selector device coupled to the memory element;

a first memory access line coupled to the memory cell;

a second memory access line coupled to the memory cell; and

a control logic configured to provide control signals for a programming pulse of the memory cell and the selector device,

wherein a portion of the programming pulse is provided to the memory cell to change a material concentration in the selector device, and

wherein the another portion of the programming pulse is provided to program a logic state of the memory element.

2. The apparatus of claim 1 , wherein the other portion of the programming pulse provided to program the logic state of the memory element comprises a current magnitude or a voltage magnitude.

3. The apparatus of claim 1 , wherein the portion of the programming pulse that is configured to change the material concentration in the selector device comprises a first polarity and the other portion of the programming pulse provided to program the logic state of the memory element comprises a second polarity.

4. The apparatus of claim 1 , wherein the first memory access line and the second memory access line are set to either a forward polarity or reverse polarity.

5. The apparatus of claim 1 , wherein the portion of the programming pulse that is configured to change the material concentration in the selector device corresponds to a change to a uniform concentration of a material in the selector device.

6. The apparatus of claim 5 , wherein the change in the uniform concentration of the material in the selector device includes a change to the material in a top portion of the selector device and a change to the material in a bottom portion of the selector device.

7. The apparatus of claim 6 , wherein the change to the material in the top portion of the selector device corresponds to changing the top portion of the selector device to have a higher concentration of Se than As in the material comprising an As—Se alloy.

8. The apparatus of claim 6 , wherein the change to the material in the bottom portion of the selector device corresponds to changing the bottom portion of the selector device to have a higher concentration of As than Se in the material comprising an As—Se alloy.

9. The apparatus of claim 5 , wherein the portion of the programming pulse that is configured to change the material concentration in the selector device includes not changing a material concentration of the memory element, such that a material concentration of the memory element remains substantially uniform.

10. The apparatus of claim 5 , wherein the portion of the programming pulse that is configured to change the material concentration in the selector device comprises a current magnitude or a voltage magnitude.

11. The apparatus of claim 1 , wherein the memory element comprises a phase change material and the programming pulse is configured by the control logic to change a phase of at least a portion of the phase change material.

12. An apparatus, comprising:

a memory element configured to receive a programming pulse including a portion to write a logic state to the memory element; and

a selector device coupled to the memory element and configured to receive the programming pulse,

wherein another portion of the programming pulse having substantially a same duration as the portion of the programming pulse causes a change to a material state in the selector device.

13. The apparatus of claim 12 , wherein the memory element is configured to receive a read pulse across the memory cell, the read pulse comprising a square shape, a triangular shape, a trapezoidal shape, a staircase shape, or a sinusoidal shape.

14. The apparatus of claim 12 , further comprising a memory array including a plurality of memory cells and a plurality of memory access lines coupled to at least some of the plurality of memory cells, wherein the memory element and selector device are included in a memory cell of the plurality of memory cells.

15. The apparatus of claim 12 , wherein the memory array is a two-dimensional array (2D) or a three-dimensional (3D) array.

16. The apparatus of claim 12 , wherein the selector device comprises a chalcogenide material.

17. A method comprising:

applying a portion of a programming pulse across a memory cell; and

applying another portion of the programming pulse to change a material of a selector device coupled to the memory cell,

wherein applying the another portion of the programming pulse to change the material of the selector device comprises altering a material concentration of the selector device.

18. The method of claim 17 , wherein applying the portion of the programming pulse across the memory cell comprises writing a logic state to the memory cell.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 13, 2017
From: PIROVANO, AGOSTINO; TORTORELLI, INNOCENZO; PELLIZZER, FABIO; REDAELLI, ANDREA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044390/0690 →
Continuity (2)
Continuation 15338154 · Oct 28, 2016
Related Publication 20180122472A1 · May 3, 2018
Cited By (1)
US 12,400,710