Uninterrupted read of consecutive pages for memory
View Patent ↗Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
1. A method comprising:
fetching words of a first page of data stored in a page buffer based at least in part on receiving an additional portion of a memory address of the first page of data;
monitoring a count of the words fetched from the page buffer; and
sensing a second page of data, before completing fetching the words of the first page of data, based at least in part on monitoring the count of the words fetched from the page buffer.
2. The method of claim 1 , wherein the second page of data is sensed in response to the count satisfying a threshold.
3. The method of claim 1 , further comprising:
receiving a first portion of the memory address of a first page before fetching the words of the first page of data stored in the page buffer.
4. The method of claim 3 , wherein the first portion of the memory address comprises bits of the memory address to identify the words of the first page of data.
5. The method of claim 1 , further comprising:
sending the second page of data to the page buffer based at least in part on one word of the words of the first page of data.
6. The method of claim 1 , further comprising:
adjusting the additional portion of the memory address between a first value and a second value, wherein the fetching the words of the first page of data is performed based at least in part on adjusting the additional portion of the memory address between the first value and the second value.
7. The method of claim 1 , wherein the additional portion of the memory address of the first page of data is received before receiving an address of the second page of data.
8. The method of claim 1 , wherein the additional portion of the memory address comprises at least one least significant bit corresponding to at least one word of the first page of data.
9. A memory device comprising:
a page buffer;
a memory cell;
a controller coupled with the page buffer and the memory cell, the controller operable to:
fetch words of a first page of data stored in the page buffer in response to receiving an additional portion of a memory address of the first page of data;
monitor a count of the words fetched from the page buffer; and
sense a second page of data before completing fetching the words of the first page of data.
10. The memory device of claim 9 , wherein the controller is further operable to:
receive a first portion of the memory address of a first page before fetching the words of the first page of data stored in the page buffer.
11. The memory device of claim 10 , wherein the first portion of the memory address comprises an address of the first page of data, and the additional portion of the memory address comprises at least one least significant bit corresponding to at least one word of the first page of data.
12. The memory device of claim 9 , wherein the controller is further operable to:
read a subsequent page of data, in response to the count reaching a threshold, while continuing to fetch the words.
13. The memory device of claim 12 , wherein the controller is adapted to:
send the subsequent page of data to the page buffer in response to at least one word of the first page of data being fetched.
14. The memory device of claim 12 , wherein the controller is operable to:
transfer the subsequent page of data to the page buffer based at least in part on fetching the words of the first page of data stored in the page buffer.
15. The memory device of claim 9 , wherein the controller is adapted to:
adjust the additional portion of the memory address between two values based at least in part on fetching the words of the first page of data stored in the page buffer.
16. The memory device of claim 9 , wherein fetching the words of the first page of data is performed in response to changing a value of the additional portion of the memory address.
17. A system comprising:
a memory device comprising an array of memory cells, the memory device further comprising a controller to:
read a page of data associated with a memory cell of the array of memory cells and flush the page of data to be stored in a page buffer;
fetch words of the page of data stored in the page buffer in response to flushing the page of data;
monitor a count of the words fetched from the page buffer; and
sense a subsequent page of data based at least in part on the monitoring the count of the words; and
a processor to initiate a write command to the controller to provide access to the array of memory cells.
18. The system of claim 17 , wherein the controller is adapted to:
read the subsequent page of data based at least in part on the count reaching a threshold.
19. The system of claim 17 , wherein the controller is adapted to:
initiate sensing of the subsequent page of data without receiving an address for the subsequent page of data.
20. The system of claim 19 , wherein the subsequent page of data comprises least significant bits of a memory address of the subsequent page of data.