Decision feedback equalizer
A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
1. A device, comprising:
a combinational circuit, comprising:
a first input configured to receive an input signal;
a second input configured to receive a reference signal;
a first clocked circuit configured to utilize a clock signal to generate an adjusted input signal based upon the input signal and an adjusted reference signal based upon the reference signal;
a third input configured to receive a first adjustment signal; and
a first clocked output configured to utilize the clock signal to transmit a corrected signal, wherein the corrected signal is based on the adjusted input signal, the adjusted reference signal, and the first adjustment signal; and
a selection circuit coupled to the combinational circuit, comprising:
a fourth input configured to receive the corrected signal;
a fifth input configured to receive a second adjustment signal; and
an output configured to selectively output the corrected signal based on the second adjustment signal.
2. The device of claim 1 , wherein the first adjustment signal is determined based upon one or more previous signals received prior to receiving the input signal.
3. The device of claim 2 , wherein the first adjustment signal can be scaled by a digital to analog converter.
4. The device of claim 1 , wherein the selection circuit comprises a multiplexer.
5. The device of claim 1 , wherein the selection circuit is configured to output the corrected signal to a deserializer as selected based on the second adjustment signal having a first value.
6. The device of claim 5 , wherein the selection circuit is configured to output a second corrected signal to the deserializer as selected based on the second adjustment signal having a second value.
7. The device of claim 6 , where in the deserializer is configured to output a value indicative of whether the first corrected signal or the second corrected value was received.
8. The device of claim 1 , wherein the first adjustment signal is generated to offset inter-symbol interference from a previous signal received prior to receiving the input signal.
9. The device of claim 1 , wherein the combinational circuit is configured to determine a logic level of the input signal utilizing the reference signal.
10. The device of claim 9 , wherein the reference signal comprises a threshold value based in part on a previously received input signal having a voltage high level.
11. The device of claim 1 , wherein the input signal comprises a distorted bit from a data stream.
12. A method, comprising:
receiving a data bit signal;
generating a modified first reference signal based upon the data bit signal in connection with a clock signal;
receiving a first reference signal indicative of a threshold value for determination of whether the data bit signal corresponds to a logical high or a logical low wherein the first reference signal corresponds to a first logical state of a previously received data bit signal;
generating a modified second reference signal based upon the first reference signal in connection with the clock signal;
applying a weighted tap value to the modified first reference signal and the modified second reference signal to generate a first adjusted bit signal;
receiving an indication of an actual logical state of the previously received data bit signal;
selecting the first adjusted data bit signal as a corrected value of the data bit signal when the actual logical state of the previously received data bit matches the first logical state of the previously received data bit signal; and
outputting the corrected value of the data bit signal.
13. The method of claim 12 , comprising receiving the corrected value of the data bit signal and storing the corrected value of the data bit signal.
14. The method of claim 13 , comprising outputting the stored corrected value of the data bit signal as an indication an actual logical state of the data bit signal.