IP Library Granted Patent US 10,360,956
Granted Patent B2
US 10,360,956 · App. 15/834,279 · Granted Jul 23, 2019

Wave pipeline

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Quick Facts
Patent No.
US 10,360,956
App. No.
15/834,279
Granted
Jul 23, 2019
Kind
B2
Abstract

A wave pipeline includes a first stage, a plurality of second stages, and a third stage. The first stage receives a data signal representative of data and a clock signal, and may process the data at a first data rate equal to a clock rate of the clock signal. Each second stage may process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages. The third stage may process data received from each second stage at the first data rate. The first stage divides the data signal and the clock signal between the plurality of second stages. The third stage merges the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

Claims (4)

1. A wave pipeline comprising: a first stage to receive a data signal representative of data and a clock signal, and to process the data at a first data rate equal to a clock rate of the clock signal; a plurality of second stages coupled in parallel, each second stage of the plurality of second stages to process respective data in response to a respective clock cycle received from the first stage at a second data rate equal to the first data rate times the number of second stages of the plurality of second stages; and a third stage to process data received from each second stage at the first data rate, wherein the first stage is to divide the data signal and the clock signal between the plurality of second stages to provide the respective data and the respective clock cycle to each of the plurality of second stages, and wherein the third stage is to merge the respective data and the respective clock cycles from each of the plurality of second stages to provide a merged data signal and a return clock signal.

2. The wave pipeline of claim 1 , further comprising: a data latch to latch the data from the third stage into the data latch in response to the return clock signal.

3. The wave pipeline of claim 1 , wherein a delay of the clock signal through each of the first stage, the plurality of second stages, and the third stage equals a delay of the data through each of the first stage, the plurality of second stages, and the third stage, respectively.

4. The wave pipeline of claim 1 , wherein the number of second stages is greater than two.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2017
From: SHAKERI, KAVEH; GHALAM, ALI FEIZ ZARRIN; TANG, QIANG; LEE, ERIC N.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044326/0977 →