IP Library Granted Patent US 10,446,566
Granted Patent B2
US 10,446,566 · App. 15/843,509 · Granted Oct 15, 2019

Integrated assemblies having anchoring structures proximate stacked memory cells

Inventors: Kunal R. Parekh (Boise, ID); Justin B. Dorhout (Boise, ID); Nancy M. Lomeli (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/11556G11C16/0483G11C16/08H01L27/1157H01L27/11519H01L27/11524H01L27/11565H01L27/11582H01L29/7883
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Quick Facts
Patent No.
US 10,446,566
App. No.
15/843,509
Granted
Oct 15, 2019
Kind
B2
Abstract

Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Claims (15)

1. An assembly, comprising:

a conductive structure over an insulative material, the conductive structure having a first region over an uppermost surface of the insulative material and having second regions that extend to an elevation below the uppermost surface of the insulative material;

channel material structures over the conductive structure within the first region, the channel material structures penetrating partially through the conductive structure and including channel material which is electrically coupled with the conductive structure; and

anchor structures laterally offset from the channel material structures, the anchor structures penetrating into the conductive structure within the second regions to a depth which is deeper than any depth to which the channel material structures penetrate into the conductive structure.

2. The assembly of claim 1 wherein the channel material structures include regions which penetrate into the conductive structure to a first depth; and wherein the depth to which the anchor structures penetrate into the conductive structure is a second depth.

3. The assembly of claim 2 wherein the second depth is at least about 30 nm deeper than the first depth.

4. The assembly of claim 2 wherein the anchor structures are insulative.

5. The assembly of claim 2 wherein the anchor structures include conductive material.

6. The assembly of claim 2 wherein the channel material structures comprise silicon.

7. The assembly of claim 2 wherein the channel material structures are configured as upwardly-opening containers.

8. The assembly of claim 2 wherein the channel material structures are configured as solid pillars.

9. The assembly of claim 2 wherein a plurality of the channel material structures is arranged in a row extending along a first direction; wherein said plurality of the channel material structures is laterally between a first of the anchor structures and a second of the anchor structures; and wherein the first and second anchor structures are configured as rails extending along a second direction substantially orthogonal to the first direction.

10. The assembly of claim 9 wherein the conductive structure includes a first conductive material over a second conductive material; wherein the row of the channel material structures is over a region of the conductive structure between the anchor structures; wherein the first conductive material has a primary thickness along said region; wherein the channel material structures do not penetrate to deeper than the primary thickness of the first conducive material; and wherein the anchor structures do penetrate to deeper than the primary thickness of the first conductive material.

11. The assembly of claim 10 wherein the first conductive material comprises conductively-doped semiconductor material, and the second conductive material comprises metal.

12. The assembly of claim 1 wherein the conductive structure, anchor structures and channel material structures are part of a memory tier; and further comprising a CMOS tier under the memory tier and having CMOS circuitry coupled with the conductive structure.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2017
From: PAREKH, KUNAL R.; DORHOUT, JUSTIN B.; LOMELI, NANCY M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044407/0639 →
Cited By (1)
US 12,293,979