I/O buffer offset mitigation
View Patent ↗Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
1. A method of operating an integrated circuit device, comprising:
applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer;
determining whether the I/O buffer is deemed to exhibit offset; and
applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset;
wherein applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer comprises:
connecting the first input of the I/O buffer to the second input of the I/O buffer; and
applying the particular voltage level to the first input of the I/O buffer while the first input of the I/O buffer is connected to the second input of the I/O buffer.
2. The method of claim 1 , wherein the I/O buffer is an input buffer, and wherein applying the particular voltage level of the first input of the I/O buffer comprises applying the particular voltage level to a conductive node of the integrated circuit device configured for connection to a device external to the integrated circuit device.
3. The method of claim 1 , further comprising:
while applying the particular voltage level to the first input of the I/O buffer, isolating the second input of the I/O buffer from a voltage node.
4. A method of operating an integrated circuit device, comprising:
connecting a first input of an input buffer of the integrated circuit device to a second input of the input buffer;
applying a particular voltage level to the first input of the input buffer;
determining whether the I/O buffer is deemed to exhibit offset;
applying an adjustment to the I/O buffer offset while the first input of the input buffer is connected to the second input of the input buffer if the input buffer is deemed to exhibit offset;
increasing a magnitude of the adjustment until a logic level of an output of the input buffer transitions; and
in response to the transition, storing trim settings for the integrated circuit device corresponding to the adjustment resulting in the transition.
5. The method of claim 4 , further comprising:
while applying the particular voltage level to the first input of the input buffer, isolating the second input of the input buffer from a voltage node.