Semiconductor device assemblies including multiple stacks of different semiconductor dies
View Patent ↗A semiconductor device assembly is provided. The assembly comprises a package substrate, a first stack of semiconductor dies having a first set of planform dimensions disposed over a first location on the substrate, a second stack of semiconductor dies having a second set of planform dimensions different from the first set disposed over a second location on the substrate, and an encapsulant at least partially encapsulating the substrate, the first stack and the second stack. The first stack of semiconductor dies has a first planform area, the second stack of semiconductor dies has a second planform area, and a sum of the first and second planform areas can be at least 50%, 67%, 75%, or even more of an area of the package substrate.
1. A semiconductor device assembly, comprising:
a package substrate having an upper surface with an upper surface area;
a first stack of semiconductor dies disposed over a first region on the substrate, each semiconductor die of the first stack of semiconductor dies having a same first length and a same first width;
a second stack of semiconductor dies disposed over a second region on the substrate, each semiconductor die of the second stack of semiconductor dies having a same second length and a same second width; and
an encapsulant at least partially encapsulating the substrate, the first stack and the second stack,
wherein the first length is different than the second length and the second width, and
wherein the first region has a first area, the second region has a second area, and a sum of the first and second areas is at least 90% of the upper surface area of the upper surface of the package substrate.
2. The semiconductor device assembly of claim 1 , wherein the first width is different than the second length and the second width.
3. The semiconductor device assembly of claim 1 , wherein the first stack of semiconductor dies is connected to the package substrate by a first plurality of wirebonds and the second stack of semiconductor dies is connected to the package substrate by a second plurality of wirebonds.
4. The semiconductor device assembly of claim 1 , wherein the first stack of semiconductor dies includes through substrate vias.
5. The semiconductor device assembly of claim 4 , wherein the second stack of semiconductor dies includes through substrate vias.
6. The semiconductor device assembly of claim 1 , wherein the first stack of semiconductor dies comprises a first plurality of memory dies, and wherein the second stack of semiconductor dies comprises a second plurality of memory dies.
7. The semiconductor device assembly of claim 6 , wherein the first plurality of memory dies and the second plurality of memory dies comprise a single memory type.
8. The semiconductor device assembly of claim 7 , wherein the single memory type is one of NAND flash, NOR flash, DRAM, PCM, FeRAM, or MRAM.
9. The semiconductor device assembly of claim 1 , wherein the package substrate includes a plurality of external connectors operably connected to the first and second stacks of semiconductor dies.
10. A method of making a memory device, comprising:
providing a substrate having an upper surface with an upper surface area;
stacking a first plurality of semiconductor dies over a first region of the substrate in a first stack, each of the first plurality of semiconductor dies having a same first length and a same first width;
stacking a second plurality of semiconductor dies different from the first set over a second region of the substrate in a second stack, each of the second plurality of semiconductor dies having a same second length and a same second width; and
providing an encapsulant to at least partially encapsulate the substrate, the first stack and the second stack,
wherein the first length is different than the second length and the second width, and
wherein the first region has a first area, the second region has a second planform area, and a sum of the first and second areas is at least 90% of the upper surface area of the upper surface of the package substrate.
11. The method of claim 10 , wherein the first width is different than the second length and the second width.
12. The method of claim 10 , wherein the first stack of semiconductor dies comprises a first plurality of memory dies, and wherein the second stack of semiconductor dies comprises a second plurality of memory dies.
13. The method of claim 12 , wherein the first plurality of memory dies and the second plurality of memory dies comprise a single memory type.