Semiconductor package and method for fabricating the same
View Patent ↗A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.
1. A semiconductor package comprising:
a first semiconductor device;
a first redistribution layer disposed beneath the first semiconductor device and electrically connected to the first semiconductor device, the first redistribution layer comprising:
a first dielectric layer; and
first discrete conductive routes extending through the first dielectric layer, wherein at least one conductive route of the first discrete conductive routes extends between and connects the first semiconductor device to a second semiconductor device;
a first molding compound disposed over the first redistribution layer and surrounding the first semiconductor device, at least a portion of the first molding compound being disposed between the first semiconductor device and the first redistribution layer and abutting against the first redistribution layer;
a second molding compound surrounding the first redistribution layer and at least a part of the first molding compound;
conductive vias extending through the second molding compound; and
a second redistribution layer disposed beneath a surface of the second molding compound away from the first redistribution layer and electrically connected to the first redistribution layer through the conductive vias.
2. The semiconductor package of claim 1 , further comprising a dielectric layer disposed on the surface of the first redistribution layer away from the first molding compound, wherein the conductive vias are further extended through the dielectric layer.
3. The semiconductor package of claim 2 , wherein at least one of a dielectric coefficient of the dielectric layer, a dielectric coefficient of the first redistribution layer, and a dielectric coefficient of the second redistribution layer is different from the others of the dielectric coefficients.
4. The semiconductor package of claim 1 , wherein a glass transition temperature of the first molding compound is greater than a glass transition temperature of the second molding compound.
5. The semiconductor package of claim 1 , wherein a smallest pitch width of the first redistribution layer is distinct from a smallest pitch width of the second redistribution layer.
6. The semiconductor package of claim 1 , wherein a surface of each of the first and second semiconductor devices, a surface of the first molding compound, and a surface of the second molding compound faced away from the second redistribution layer are coplanar.
7. The semiconductor package of claim 1 , further comprising conductive bumps extended through the first molding compound, to electrically connect the first redistribution layer to the first semiconductor device.
8. The semiconductor package of claim 1 , further comprising solder balls disposed on a surface of the second redistribution layer away from the second molding compound, wherein the solder balls are connected to the second redistribution layer respectively.
9. A method for fabricating a semiconductor package comprising:
providing a workpiece, wherein the workpiece comprising a first redistribution layer, conductive vias and a first wafer, the conductive vias are extended into the first wafer, the first redistribution layer being disposed on the first wafer, connected to the conductive vias, and comprising first discrete conductive routes formed therein;
disposing a first semiconductor device on a side of the first redistribution layer away from the conductive vias;
disposing a second semiconductor device on the side of the first redistribution layer away from the conductive vias, the first discrete conductive routes extending between and connecting the first semiconductor device to the second semiconductor device, the first and second semiconductor devices being connected to the first redistribution layer;
forming a first molding compound to surround the first and second semiconductor devices such that at least a portion of the first molding compound is disposed between the first semiconductor device and the first redistribution layer and abuts against the first redistribution layer;
removing the first wafer;
forming a second molding compound to surround the first redistribution layer and at least part of the first molding compound, wherein the conductive vias are exposed on a surface of the second molding compound away from the first redistribution layer; and
forming a second redistribution layer on a surface of the second molding compound away from the first redistribution layer and electrically connected to the first redistribution layer through the conductive vias.
10. The method of claim 9 , further comprising:
depositing a dielectric layer on the first wafer;
forming trenches extending through the dielectric layer and extending into the first wafer; and
filling the trenches with a conductive material to form the conductive vias.
11. The method of claim 9 , further comprising:
singulating the first and second semiconductor devices through the first molding compound and the first redistribution layer.
12. The method of claim 9 , further comprising:
singulating through the first molding compound and the first redistribution layer to separate the first semiconductor device form the second semiconductor device.
13. The method of claim 9 , further comprising:
disposing the first and second semiconductor devices onto a second wafer after the removing of the first wafer.
14. The method of claim 9 , wherein a smallest pitch width of the first redistribution layer is distinct from a smallest pitch width of the second redistribution layer.
15. The method of claim 9 , wherein materials of the first molding compound is differed from materials of the second molding compound.
16. The method of claim 9 , further comprises:
forming solder balls on the second redistribution layer.
17. The semiconductor package of claim 1 , wherein the first redistribution layer is encapsulated by the first molding compound and the second molding compound.
18. The semiconductor package of claim 1 , wherein the first redistribution layer further comprises:
a second dielectric layer in contact with the first dielectric layer and having the first discrete conductive routes formed therein.
19. The method of claim 9 , wherein forming the first and second molding compounds comprises encapsulating the first redistribution layer with the first and second molding compounds.
20. The semiconductor package of claim 18 , where in the first dielectric layer is in contact with the first molding compound.