Techniques for sensing logic values stored in memory cells using sense amplifiers that are selectively isolated from digit lines

1. A method of operating a memory apparatus, comprising:

isolating a digit line from a first sensing node of a sense amplifier before sensing a voltage difference between the first sensing node and a second sensing node; and

activating the sense amplifier to amplify and sense a voltage difference between the first sensing node and the second sensing node based at least in part on the isolating.

2. The method of claim 1 , further comprising:

deactivating the sense amplifier based at least in part on sensing the voltage difference between the first sensing node and the second sensing node.

3. The method of claim 2 , further comprising:

applying a voltage on the first sensing node by coupling the digit line to the first sensing node after deactivating the sense amplifier.

4. The method of claim 1 , further comprising:

reading a logic value stored in a memory cell onto the first sensing node based at least in part on coupling the memory cell to the first sensing node.

5. The method of claim 4 , further comprising:

determining a state of the sense amplifier prior to the isolating, wherein reading the logic value is further based at least in part on determining the state of the sense amplifier.

6. The method of claim 4 , further comprising:

biasing the second sensing node of the sense amplifier to a reference voltage from a reference voltage source, wherein reading the logic value is further based at least in part on the biasing.

7. The method of claim 6 , further comprising:

isolating the reference voltage source from the second sensing node of the sense amplifier after biasing the second sensing node and before sensing a voltage difference between the first sensing node and the second sensing node.

8. A method for a read operation by a memory apparatus, comprising:

initiating a sense operation;

coupling a digit line to a first sensing node of a sense amplifier based at least in part on the initiating;

reading a logic value stored in a memory cell onto the first sensing node of the sense amplifier based at least in part on the coupling; and

isolating the digit line from the first sensing node after the reading and before sensing a voltage difference between the first sensing node and a second sensing node.

9. The method of claim 8 , further comprising:

biasing the second sensing node of the sense amplifier to a reference voltage provided by a reference voltage source, wherein the biasing is performed while reading the logic value.

10. The method of claim 8 , wherein a first voltage of the digit line, a word line, and a plate line associated with the memory apparatus are equal during a first period, wherein the first period occurs prior to the sense operation.

11. The method of claim 10 , further comprising:

applying, to the word line, a second voltage that is greater than the first voltage; and

performing a cell selection and the read operation during a second period based at least in part on the applying.

12. The method of claim 11 , wherein the second period is after the first period.

13. The method of claim 11 , further comprising:

applying, to the plate line, a third voltage during the second period, wherein the third voltage is less than the second voltage; and

applying, to a capacitor of the memory cell, the third voltage.

14. The method of claim 8 , further comprising:

determining that a voltage of the digit line is greater than or less than a reference voltage from a reference voltage source based at least in part on the logic value stored in the memory cell; and

determining that the voltage of the digit line is in a steady state, wherein initiating the sense operation is based at least in part on the voltage of the digit line being in the steady state.

15. The method of claim 8 , further comprising:

determining that a voltage applied to the first sensing node is greater than a reference voltage provided by a reference voltage source; and

amplifying the voltage of the first sensing node during the sense operation based at least in part on the logic value stored in the memory cell and determining that the voltage applied to the first sensing node is greater than the reference voltage.

16. The method of claim 8 , further comprising:

recoupling the digit line to the first sensing node after the sense operation.

17. A memory apparatus, comprising:

a sense amplifier having a first sensing node and a second sensing node; and

a controller operable to: isolate a digit line from the first sensing node of the sense amplifier before sensing a voltage difference between the first sensing node and the second sensing node; and activate the sense amplifier to amplify and sense a voltage difference between the first sensing node and the second sensing node based at least in part on the isolating.

18. The memory apparatus of claim 17 , wherein the controller is operable to:

close a first transfer gate of the plurality of transfer gates to read a logic value stored in a memory cell onto the first sensing node through the digit line;

close a second transfer gate of the plurality of transfer gates to bias the second sensing node to a reference voltage provided by a reference voltage source; and

open the first transfer gate to isolate the digit line from the first sensing node based at least in part on closing the first transfer gate.

19. The memory apparatus of claim 18 , wherein the controller is operable to:

deactivate the sense amplifier based at least in part on sensing the voltage difference between the first sensing node and the second sensing node.

20. The memory apparatus of claim 19 , wherein the controller is operable to:

close the first transfer gate to couple the digit line to the first sensing node to apply a voltage on the first sensing node based at least in part on the deactivation.