Apparatuses and methods for providing data to a configurable storage area
View Patent ↗Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.
1. An apparatus, comprising:
an array having a storage area;
an extended address register including a plurality of configuration bits that define a partition of the array as the storage area;
a buffer configured to store data in a plurality of cache lines, the data including data to be stored in the storage area; and
a memory control circuit configured to control the storage area of the array to store, when the flush command is received and prior to when the flush command is interrupted to prepare for a read command or a write command, the data to be stored in the storage area.
2. The apparatus of claim 1 , wherein the memory control circuit is configured to interrupt the flush command responsive to a maximum variable latency period for the read and write commands.
3. The apparatus of claim 1 , wherein the configuration hits define the partition by a size and/or offset of the storage area relative to an address of the storage area.
4. The apparatus of claim 1 , further comprising:
a flag status register including a flush bit, the flush bit configured to indicate whether the buffer includes the data to be stored in the storage area.
5. The apparatus of claim 1 , wherein the memory control unit is further configured to identify the data to be stored in the storage area based, at least in part, on an address associated with the data to be stored in the storage area.
6. The apparatus of claim 1 , further comprising:
a host coupled to the memory control unit and configured to provide the flush command.
7. The apparatus of claim 1 , wherein the array comprises non-volatile memory.
8. The apparatus claim 1 , wherein the apparatus is included in a memory.
9. The apparatus of claim 1 , wherein the apparatus is included in a random access memory.
10. The apparatus of claim 1 , wherein the apparatus is included in a read only memory.
11. An apparatus, comprising:
an array having a storage area;
an extended address register including a plurality of configuration bits that define a partition of the array as the storage area; and
a memory control circuit configured to provide information regarding when the memory control circuit is available to perform a flush command, and further configured to control, when the memory control circuit is available to perform the flush command and when the flush command is received, the storage area of the array to store data configured to be stored in the storage area.
12. The apparatus of claim 11 , wherein the flush command is interrupted to prepare for a read command or a write command.
13. The apparatus of claim 11 , wherein information regarding an amount of time before the memory control unit is available to perform the flush command is provided by a host.
14. The apparatus of claim 11 , wherein the memory control circuit is configured to control, after the flush command is interrupted, the storage area of the array to resume the flush command to store, when a read command or a write command is performed, the data configured to be stored in the storage area.
15. The apparatus of claim 11 , wherein the flush command is interrupted to prepare for a read command or a write command, and resumed when the read command or the write command is performed.
16. The apparatus of claim 11 , wherein the apparatus is included in one of a random access memory, a read only memory, a dynamic random access memory, a synchronous dynamic random access memory, a flash memory, and a resistance variable memory.
17. An apparatus, comprising:
an array having a storage area;
a buffer coupled to the array and configured to store data in a plurality of cache lines, the data including data to be stored in the storage area based on a plurality of configuration bits configured to indicate an offset relative to a size of the array; and
a memory control circuit configured to control, the storage area of the array to store, when a flush command is received before a read command or a write command is performed, at least a portion of the data to be stored in the storage area.
18. The apparatus of claim 17 , wherein the memory control circuit is further configured to control the storage area of the array to store, once the read command or the write command is performed, a remainder of the data to be stored in the storage area.
19. The apparatus of claim 17 , further comprising:
a host coupled to the memory control unit and configured to receive information regarding whether the memory control unit is available to perform a memory operation.
20. The apparatus of claim 17 , wherein the apparatus is included in one of a flash memory and a resistance variable memory.