Systems and methods for maintaining refresh operations of memory banks using a shared
A memory device includes memory banks that each have multiple rows with row addresses. The memory device also includes a counter that stores and increments a first row address of a first row of a first set of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode. The memory device further includes circuitry that blocks incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.
1. A memory device comprising:
a plurality of memory banks, wherein each memory bank of the plurality of memory banks comprises a plurality of rows, wherein each row of the plurality of rows comprises a row address;
a counter configured to store and increment a first row address of a first row of a first set of memory banks of the plurality of memory banks to a second row address of a second row of the first set of memory banks in response to a first refresh operation when the memory device is operating in a first mode; and
circuitry configured to block incrementing the second row address to a third row address of a third row of the first set of memory banks when the memory device transitions from the first mode to a second mode and the first refresh operation is not paired with a second refresh operation that is performed when the memory device is operating in the first mode.
2. The memory device of claim 1 , wherein the first mode is configured to enable a refresh command to perform a refresh operation on one or more rows of the plurality of rows.
3. The memory device of claim 1 , wherein the second mode is configured to enable a refresh command to perform two refresh operations on two sets of rows of the plurality of rows.
4. The memory device of claim 1 , wherein the first set of memory banks is configured to be refreshed during activation of a second set of memory banks of the plurality of memory banks.
5. The memory device of claim 1 , wherein a second set of memory banks of the plurality of memory banks is configured to be refreshed during activation of the first set of memory banks.
6. The memory device of claim 1 , comprising a second counter configured to store and increment the first row address of the first row of a second set of memory banks of the plurality of memory banks to the second row address of the second row of the second set of memory banks in response to the second refresh operation when the memory device is operating in the first mode.
7. The memory device of claim 6 , wherein the circuitry is configured to increment the second row address to the third row address when the memory device transitions from the first mode to the second mode and the first refresh operation is paired with the second refresh operation that is performed when the memory device is operating in the first mode.