Signal training for prevention of metastability due to clocking indeterminacy
View Patent ↗Methods and systems that may employ adjustments to the latencies in the input circuitry to reduce the latency during initialization period and to prevent undesired effects from metastability are provided. Disclosed systems may employ adjustable delays during a signal training process to cause adjustments in the timing of the host that will reduce latencies during write cycles. Certain systems may further reduce latencies by employing input logic circuitry that produces a valid, consistent signal from the bidirectional connection, such as a gate, and preventing metastability in input circuitry altogether. Such circuitry allows bypassing of initialization periods to stabilize the input, and allows further reduction of the initialization.
1. A memory device comprising:
a command decoder configured to receive a command signal, wherein the command decoder is configured to provide a write command signal when the received command signal comprises a write operation;
a clock comparator configured to receive a differential clock signal and to provide a clock signal associated with the command signal, wherein the clock signal comprises a first latency relative to the received command signal;
a latch configured to store the command signal based on the clock signal received from the clock comparator;
a first delay element configured to provide the command signal to the latch, wherein the first delay element is configured to delay the received command signal to match the first latency;
a strobe comparator configured to receive a differential strobe signal and to provide a data strobe signal wherein the differential strobe signal is associated with a data signal received by the memory device during the write operation; and
gating circuitry configured to receive the write command signal and the data strobe signal, and to provide a gated data strobe signal.
2. The memory device of claim 1 , wherein the gating circuitry is an AND gate.
3. The memory device of claim 1 , wherein the gating circuitry is a NAND gate or a NOR gate.
4. The memory device of claim 1 , wherein the gating circuitry comprises a second latch configured to receive the write command signal and the data strobe signal and to provide a data strobe enable signal.
5. The memory device of claim 4 , wherein the gating circuitry comprises a gating element configured to receive the write command signal and a write end command signal, and to provide a gated write command signal to the second latch.
6. The memory device of claim 1 , comprising counter circuitry configured to receive the write command signal and the gated data strobe signal, and to provide a write end command signal.
7. The memory device of claim 1 , comprising a second delay element configured to receive the data strobe signal from the strobe comparator and to provide a delayed data strobe signal to the gating circuitry.
8. The memory device of claim 1 , wherein the data strobe signal comprises a double-data rate data strobe signal.
9. The memory device of claim 1 , wherein the memory device comprises a DDR5 SDRAM memory device.
10. A memory device comprising:
a command and decoder configured to receive a command and address signal and to provide a write command that initiates a write burst;
gating circuitry configured to receive a data strobe signal and the write command, and to provide a gated data strobe signal during the write burst, wherein the gated data strobe signal comprises a fixed voltage signal when the data strobe signal is not driven during initiation of the write burst; and
counting circuitry configured to receive the gated data strobe signal and to provide a write end command to the gating circuitry.
11. The memory device of claim 10 comprising a first delay element configured to delay the received command and address signal during a signal training mode to cause a host circuitry coupled to the memory device to advance a transmission of the data strobe signal.
12. The memory device of claim 10 , wherein the counting circuitry comprises a 4-bit mode and a 8-bit mode.
13. The memory device of claim 10 , wherein the counting circuitry comprises a plurality of flip-flops arranged in a cascade.
14. The memory device of claim 10 , comprising a cyclic-redundancy check (CRC) circuitry.
15. The memory device of claim 10 , wherein the gating circuitry comprises:
latch circuitry that receives the data strobe signal, the write command, and the write end command, and provides a gate enable signal; and
a gate configured to receive the data strobe signal and the gate enable signal, and to provide the gated data strobe signal.
16. The memory device of claim 10 , wherein the memory device comprises a DDR5 SDRAM device.
17. A method to prevent metastability in a memory device, comprising:
performing a signal training routine, the method comprising:
receiving an instruction signal comprising a write operation from a host device;
decoding the write operation to create a write command in a decoder of the memory device;
receiving a data strobe signal from the host device; and
advancing a feedback of the signal training routine to the host device in response to the data strobe signal to cause the host device to delay the data strobe signal; and
receiving data from the host device during a write instruction, the method comprising:
receiving a second instruction signal comprising the write operation from the host device;
decoding the write operation to create the write command in the decoder;
during a initialization period of the write operation, providing the write command to gating circuitry configured to receive the data strobe signal; and
gating, in the gating circuitry, the received data strobe signal based using the write command.
18. The method of claim 17 , wherein the memory device comprises a DDR5 SDRAM device, and wherein the initialization period comprises a write leveling initialization period.
19. The method of claim 17 , comprising during the signal training routine, adjusting a delay element configured to delay the instruction signal based on a skew between the instruction signal and a clock signal received in the memory device.
20. The memory device of claim 1 , wherein the first latency of the clock signal relative to the command signal is caused by the first delay element during a training operation.