Apparatuses and methods for providing frequency divided clocks

1. An apparatus, comprising:

a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock;

a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock; and

a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks, wherein the third circuit comprises:

a delay circuit configured to delay the first intermediate clock to produce a delayed intermediate clock;

a phase detector configured to compare a phase of the delayed intermediate clock and the second intermediate clock; and

a multiplexer coupled to receive the second and third intermediate clocks, the multiplexer configured to select one of the second and third intermediate clocks responsive, at least in part, to an output from a phase detector, the multiplexer comprising:

a first logic gate including a first input coupled to receive the second intermediate clock;

a first inverter circuit including an output coupled to a second input of the first logic gate;

a second logic gate including a first input coupled to receive the third intermediate clock;

a second inverter circuit including an input coupled to an output of the first inverter circuit and further including an output coupled to a second input of the second logic gate; and

a third logic gate coupled to receive outputs of the first and second logic gates and including an output from which the output clock is provided.

2. The apparatus of claim 1 ,

wherein the first intermediate clock has a frequency that is a half of a frequency of the first input clock;

wherein each of the second and third intermediate clocks has a frequency that is a half of a frequency of the second input clock; and

wherein the delay circuit is configured to delay the first intermediate clock by a half clock of the first input clock to produce the delayed intermediate clock.

3. The apparatus of claim 1 wherein the phase detector is further configured to provide an output to the multiplexer having a value indicative of a phase relationship between the delayed intermediate clock and the second intermediate clock to control selection of one of the second and third intermediate clocks.

4. The apparatus of claim 1 , wherein the delay circuit comprises at least one of a D latch and a D flip-flop clocked by complementary clocks that are based on the first input clock.

5. The apparatus of claim 1 , further comprising:

a first phase splitter coupled to receive the first input clock and provide first complementary input clocks responsive, at least in part, to the first input clock; and

a second phase splitter coupled to receive the second input clock and provide second complementary clocks responsive, at least in part, to the second input clock.

6. An apparatus, comprising:

a clock divider circuit configured to receive a first input clock and provide a first output clock responsive at least in part to the first input clock, the first output clock having a lower frequency than the first input clock, and further configured to receive a second input clock and provide a second output clock responsive at least in part to the second input clock, the second output clock having a lower frequency than the second input clock,

wherein the second output clock is selected from first and second divided clocks that are provided responsive at least in part to the second input clock,

wherein the clock divider circuit comprises:

a first divider circuit coupled to receive the first input clock and configured to provide a first divided clock having a lower clock frequency than the first input clock;

a second divider circuit coupled to receive the second input clock and configured to provide a second divided clock and a third divided clock, wherein the second and third divided clocks are complementary and have a lower clock frequency than the second input clock;

a phase detector coupled to receive a delayed first divided clock and the second divided clock and configured to provide a phase difference signal having a value based on relative phases of the delayed first divided clock and the second divided clock;

a multiplexer coupled to receive the second and third divided clocks and configured to select one of the second and third divided clocks as the second output clock based at least in part on the value of the phase difference signal; and

an output circuit coupled to receive the first divided clock and configured to provide the first output clock, the output circuit including a propagation delay matched to a propagation delay of the multiplexer.

7. The apparatus of claim 6 , further comprising:

a phase detector coupled to receive the first and second output clocks and configured to compare a phase of the first and second clocks and provide a phase difference signal having a value indicative of the phase of the first and second clocks;

a delay adjustment circuit coupled to receive the phase difference signal and the first input clock and configured to delay the first input clock based at least in part on the phase difference signal to provide a synchronized output clock; and

a replica circuit coupled to receive the synchronized output clock and configured to delay the synchronized output clock to provide the second input clock to the clock divider circuit.

8. The apparatus of claim 7 , further comprising:

a duty cycle adjuster circuit coupled to receive the first input clock and configured to correct a duty cycle of the first input clock and provide a duty cycle corrected first input clock to the delay adjustment circuit.

9. The apparatus of claim 6 , wherein the clock divider circuit further comprises a delay circuit coupled to the first divider circuit to receive the first divided clock and configured to delay the first divided clock by one-half a clock period of the first input clock to provide the delayed first divided clock.

10. The apparatus of claim 9 , wherein the clock divider circuit further comprises a dummy circuit coupled to the second divider circuit and configured to balance loading of the delay circuit.