Constructions comprising stacked memory arrays
View Patent ↗Some embodiments include a construction having a first memory array deck and a second memory array deck over the first memory array deck. The second memory array deck differs from the first memory array deck in one or more operating characteristics, in pitch, and/or in one or more structural parameters; with the structural parameters including different materials and/or different thicknesses of materials. Some embodiments include a construction having a first series and a third series of access/sense lines extending along a first direction, and a second series of access/sense lines between the first and third series and extending along a second direction which crosses the first direction. First memory cells are between the first and second series of access/sense lines and arranged in a first memory array deck. Second memory cells are between the second and third series of access/sense lines and arranged in a second memory array deck.
1. A construction, comprising:
a first memory array deck comprising phase change memory, the first memory array deck comprising memory cells that are laterally spaced from one another by a first dielectric material;
a second memory array deck over the first memory array deck, the second memory array deck comprising memory cells separated from one another by a second dielectric material; and
a first series of access/sense lines disposed vertically between the first memory array deck and the second memory array deck, the lines of the first series of access/sense lines being formed of a single material; and
a second series of access/sense lines disposed vertically above the second memory array deck, the lines of the second series of access/sense lines comprising multiple materials.
2. The construction of claim 1 wherein the first memory array deck has a different access time than the second memory array deck.
3. The construction of claim 1 wherein the first memory array deck has a different endurance than the second memory array deck.
4. The construction of claim 1 wherein the second memory array deck has faster access times than the first memory array deck; and wherein the first memory array deck has greater endurance than the second memory array deck.
5. The construction of claim 1 wherein the first series of access/sense lines are shared between the first and second memory array decks.
6. The construction of claim 1 wherein the first memory array deck has durability of at least about 10-fold more cycling times than the second memory array deck.
7. The construction of claim 1 wherein the first memory array deck comprises germanium-containing chalcogenide as programmable material of the phase change memory.
8. A construction, comprising:
a first memory array deck comprising phase change memory, the first memory array deck comprising memory cells that are laterally spaced from one another by a first dielectric material;
a second memory array deck over the first memory array deck, the second memory array deck comprising memory cells separated from one another by a second dielectric material; and
a series of access/sense lines disposed vertically between the first memory array deck and the second memory array deck; and wherein:
the first dielectric material comprises first insulative material liners along sidewalls of memory cells;
the second dielectric material comprises second insulative material liners along sidewalls of memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners.
9. The construction of claim 1 further comprising metallization over the second memory array deck and electrically coupling circuitry of the second memory array deck with circuitry peripheral to the second memory array deck.
10. The construction of claim 1 wherein access/sense lines of the first memory array deck differ from access/sense lines of the second memory array deck in one or both of composition and thickness.
11. A construction, comprising:
a first memory array deck;
a second memory array deck over the first memory array deck, the second memory array deck differing from the first memory array deck in thicknesses of materials;
a first series of access/sense lines disposed vertically between the first memory array deck and the second memory array deck, the first series of access/sense lines being formed of a metal;
a second series of access/sense lines disposed vertically above the second memory array deck, the second series of lines comprising the metal and a low resistance material;
wherein the first memory array deck comprises first memory cells that are laterally spaced from one another by first dielectric regions along a cross-section; and
wherein the second memory array deck comprises second memory cells that are laterally spaced from one another by second dielectric regions along the cross-section, the second dielectric regions having a different material thickness than the first dielectric regions.
12. The construction of claim 11 wherein:
the first memory cells comprise first programmable material;
the second memory cells comprise second programmable material; and
the first programmable material is a different thickness than the second programmable material.
13. The construction of claim 11 wherein:
the first memory cells comprise first programmable material;
the second memory cells comprises second programmable material within second memory cells; and
the first programmable material is a different composition than the second programmable material.
14. A construction, comprising:
a first memory array deck;
a second memory array deck over the first memory array deck, the second memory array deck differing from the first memory array deck in thicknesses of materials;
a series of access/sense lines disposed vertically between the first memory array deck, and the second memory array deck;
wherein the first memory array deck comprises first memory cells that are laterally spaced from one another by first dielectric regions along a cross-section; and
wherein the second memory array deck comprises second memory cells that are laterally spaced from one another by second dielectric regions along the cross-section, the second dielectric regions having a different material thickness than the first dielectric regions; and wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different thicknesses than the second insulative material liners.
15. A construction, comprising:
a first memory array deck:
a second memory array deck over the first memory array deck, the second memory array deck differing from the first memory array deck in thicknesses of materials;
a series of access/sense lines disposed vertically between the first memory array deck and the second memory array deck;
wherein the first memory array deck comprises first memory cells that are laterally spaced from one another by first dielectric regions along a cross-section; and
wherein the second memory array deck comprises second memory cells that are laterally spaced from one another by second dielectric regions along the cross-section, the second dielectric regions having a different material thickness than the first dielectric regions; and wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells; and
the first insulative material liners are different compositions than the second insulative material liners.
16. The construction of claim 11 wherein:
the first dielectric regions comprise first insulative material liners along sidewalls of the first memory cells;
the first dielectric regions comprise a first insulator between the first insulative material liners;
the second dielectric regions comprise second insulative material liners along sidewalls of the second memory cells;
the second dielectric regions comprise a second insulator between the second insulative material liners; and
wherein the second insulator is a different composition relative to the first insulator.
17. The construction of claim 11 wherein the series of access/sense lines are shared between the first and second memory array decks.
18. The construction of claim 11 wherein access/sense lines of the first memory array deck differ from access/sense lines of the second memory array deck in one or both of composition and thickness.