Methods for independent memory bank maintenance and memory devices and systems employing the same
View Patent ↗Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.
1. A memory device, comprising:
a plurality of memory banks; and
circuitry configured to:
store a plurality of values, each value of the plurality of values corresponding to one memory bank of the plurality of memory banks,
refresh first data stored in a first memory bank of the plurality of memory banks, and
update a first value of the plurality of values corresponding to the first memory bank of the plurality of memory banks based at least in part on refreshing the first data.
2. The memory device of claim 1 , wherein the circuitry is further configured to:
subsequent to refreshing the first data, and before refreshing data stored in all of the other memory banks of the plurality of memory banks, refresh second data in the first memory bank of the plurality of memory banks, and
update the first value of the plurality of values based at least in part on refreshing the second data.
3. The memory device of claim 2 , wherein the second data corresponds to a second row of the first memory bank of the plurality of memory banks.
4. The memory device of claim 1 , wherein the first data corresponds to a first row of the first memory bank of the plurality of memory banks.
5. The memory device of claim 1 , wherein each of the plurality of values corresponds to a row address in a corresponding memory bank of the plurality of memory banks.
6. The memory device of claim 5 , wherein the circuitry is configured to update the first value of the plurality of values by replacing the row address of the refreshed first data with another row address of the corresponding memory bank of the plurality of memory banks.
7. The memory device of claim 1 , wherein the circuitry is further configured to:
refresh second data stored in a second memory bank of the plurality of memory banks; and
update a second value of the plurality of values corresponding to the second memory bank of the plurality of memory banks based at least in part on refreshing the second data.
8. The memory device of claim 1 , wherein a single semiconductor die comprises the plurality of memory banks and the circuitry.
9. The memory device of claim 1 , wherein the plurality of memory banks comprise dynamic random access memory (DRAM) banks, ferroelectric random access memory (FeRAM) banks, magnetoresistive memory (MRAM) banks, phase change memory (PCM) banks, or a combination thereof.