Array of cross point memory cells
A method of forming an array of memory cells comprises forming an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines, and programmable material of individual inner tier memory cells elevationally between the inner tier first lines and the inner tier second lines where such cross. First insulative material is formed laterally between the inner tier second lines to have respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier second lines. Second insulative material is formed elevationally over the first insulative material and laterally between the inner tier second lines. The second insulative material is of different composition from that of the first insulative material. An elevationally outer tier of memory cells is formed to comprise spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines, and programmable material of individual outer tier memory cells elevationally between the outer tier first lines and the outer tier second lines where such cross. Arrays of memory cells independent of method of manufacture are disclosed.
1. An array of memory cells, comprising:
an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines crossing the inner tier lower first conductive lines, and programmable material elevationally between the inner tier lower first conductive lines and the inner tier upper second conductive lines at respective locations where such cross;
first insulative material laterally between the inner tier upper second conductive lines having respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier upper second conductive lines, the respective elevationally outermost surfaces of the first insulative material being elevationally outward of elevationally innermost surfaces of the inner tier upper second conductive lines;
second insulative material elevationally over the first insulative material and laterally between the inner tier upper second conductive lines, the second insulative material being of different composition from that of the first insulative material, the second insulative material and the inner tier upper second conductive lines having respective elevationally outermost surfaces that are elevationally coincident;
an elevationally outer tier of memory cells comprising spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines crossing the outer tier lower first conductive lines, and programmable material of elevationally between the outer tier lower first conductive lines and the outer tier upper second conductive lines at respective locations where such cross;
third insulative material above and directly against the second insulative material laterally between the spaced outer tier lower first conductive lines, the third insulative material being of different composition from that of the second insulative material, the third insulative material having respective elevationally innermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the outer tier lower first conductive lines; and
the spaced outer tier lower first conductive lines and the spaced inner tier upper second conductive lines comprising differing materials relative to each other and together forming respective shared conductive lines having vertically-continuous conductive material from tops to bottoms of the respective shared conductive lines, each of the shared conductive lines comprising a lower portion consisting of the respective inner tier upper second conductive line and an upper portion consisting of respective outer tier lower first conductive line, the second insulative material being in direct physical contact with the vertically-continuous conductive material only along the lower portion.
2. The array of claim 1 wherein the third insulative material is of the same composition as the first insulative material.
3. The array of claim 1 wherein the first insulative material comprises at least 10% atomic carbon and the second insulative material comprises less than 1% atomic, if any, carbon.
4. The array of claim 1 wherein the respective elevationally outermost surfaces of the second insulative material and the respective elevationally outermost surfaces of the inner tier second conductive lines are everywhere planar and thereby coplanar.
5. The array of claim 1 wherein individual ones of the inner tier upper second conductive lines and individual ones of the outer tier lower first conductive lines are electrically shared by the elevationally inner and outer tiers.
6. The array of claim 1 wherein the first insulative material comprises at least 25% atomic carbon and the second insulative material comprises less than 1% atomic, if any, carbon.
7. The array of claim 1 wherein the respective shared conductive lines have continuous vertical sidewalls from their respective tops to their respective bottoms.
8. An array of memory cells, comprising:
an elevationally inner tier of memory cells comprising spaced inner tier lower first conductive lines, spaced inner tier upper second conductive lines crossing the inner tier lower first conductive lines, and programmable material elevationally between the inner tier lower first conductive lines and the inner tier upper second conductive lines at respective locations where such cross, the programmable material being in direct physical contact with the inner tier upper second conductive lines;
first insulative material laterally between the inner tier upper second conductive lines having respective elevationally outermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the inner tier upper second conductive lines, the respective elevationally outermost surfaces of the first insulative material being elevationally outward of elevationally innermost surfaces of the inner tier upper second conductive lines;
second insulative material elevationally over the first insulative material and laterally between the inner tier upper second conductive lines, the second insulative material being of different composition from that of the first insulative material, the second insulative material and the inner tier upper second conductive lines having respective elevationally outermost surfaces that are elevationally coincident;
an elevationally outer tier of memory cells comprising spaced outer tier lower first conductive lines, spaced outer tier upper second conductive lines crossing the outer tier lower first conductive lines, and programmable material of elevationally between the outer tier lower first conductive lines and the outer tier upper second conductive lines at respective locations where such cross;
a third insulative material above and directly against the second insulative material laterally between the spaced outer tier lower first conductive lines, the third insulative material being of different composition from that of the second insulative material, the third insulative material having respective elevationally innermost surfaces that are lower than elevationally outermost surfaces of immediately laterally-adjacent of the outer tier lower first conductive lines; and
the spaced outer tier lower first conductive lines and the spaced inner tier upper second conductive lines together forming respective shared conductive lines having vertically-continuous conductive material from tops to bottoms of the respective shared conductive lines, each of the shared conductive lines comprising a lower portion consisting of the respective inner tier upper second conductive line and an upper portion consisting of respective outer tier lower first conductive line, the second insulative material being in direct physical contact with the vertically-continuous conductive material only along the lower portion.
9. The array of claim 8 further comprising a select device material between the programmable material and the inner tier lower first conductive lines.