Transistors and memory arrays

1. A method of forming a transistor, comprising:

forming a semiconductor material panel between a first insulative material panel and a second insulative material panel; the first insulative material panel having a first trench extending downwardly therein and the second insulative material panel having a second trench extending downwardly therein; the semiconductor material comprising a first post region and a second post region; the semiconductor material further comprising a fin region extending between the first and second post regions; each of the first and second post regions having a first thickness and the fin region having a second thickness, with the second thickness being less than the first thickness; the fin region comprising a lower part and an upper part that protrudes from the lower part; at least one of a pair of side surfaces of the fin region being substantially uneven at a connection portion between the lower part and the upper part;

forming gate dielectric material along and against sidewalls of the first and second post regions, along a top surface of the fin region, and along the side surfaces of the fin region;

forming gate material along the sidewalls of the first and second post regions, the top surface of the fin region and the side surfaces of the fin region;

forming a first source/drain region within the first post region; and

forming a second source/drain region within the second post region.

2. The method of claim 1 wherein the first and second insulative material panels have downwardly-extending edges along sides of the first and second trenches, and wherein the first and second post regions are inset from the downwardly-extending edges of the first and second insulative material panels by a distance of at least about 2 nm.

3. The method of claim 1 wherein the second thickness is within a range of from about 2 nm to about 20 nm; and wherein the first thickness is within a range of from about 5 nm to about 50 nm.

4. The method of claim 1 wherein the and second insulative material panels are a same composition as one another.

5. The method of claim 4 wherein the and second insulative material panels comprise silicon dioxide.

6. The method of claim 1 wherein the semiconductor material panel comprises silicon.

7. The method of claim 1 , wherein the first and second post regions are elongated structures comprising upper terminal ends elevational above upper terminal ends of the fin region.

8. The method of claim 1 , wherein the first and second trenches expose an upper surface of the fin region comprising an H configuration.

9. The method of claim 1 , wherein the first and second insulative material panels comprise sides that extend to upper terminal ends that are coplanar and against entire sides and upper terminal ends of the semiconductor material panel.

10. The method of claim 1 , wherein the first and second posts comprises a pair of separate and discrete structures that extend elevational above the fin region and are devoid of the semiconductor material between the pair of the separate and discrete structures.

11. The method of claim 1 , wherein the forming of the gate dielectric material comprises forming the gate dielectric material against the side surfaces of the fin region.

12. The method of claim 1 , wherein the direction of the first and second thicknesses are perpendicular to the direction between the first and second post regions.

13. A method comprising:

forming first and second insulative materials to define a semiconductor panel between the first and second insulative materials, wherein the first insulative material, the semiconductor panel and the second insulative material are arranged in a first direction, wherein the first insulative material includes a first trench and first and second portions sandwiching the first trench in a second direction crossing the first direction, wherein the second insulative material includes a second trench and third and fourth portions sandwiching the second trench in the second direction, and wherein the semiconductor panel includes a first post region between the first portion of the first insulative material and the third portion of the second insulative material, a fin region between the first and second trenches and a second post region between the second portion of the first insulative material and the fourth portion of the second insulative material; and

selectively etching the semiconductor panel, wherein the selectively etching the semiconductor panel comprises thinning the fin region in the first direction to provide a narrow fin region comprising a linear middle portion extending between two end portions that extend perpendicularly to the linear middle portion.

14. The method of claim 13 , wherein the selectively etching the semiconductor panel further comprises removing respective parts of the first and second post regions in the second direction to provide a first inset gap between the first portion of the first insulative material and the narrow fin region and a second inset gap between the second portion of the first insulative material and the narrow fin region.

15. The method of claim 14 , wherein the selectively etching the semiconductor panel further comprises removing respective other parts of the first and second post regions in the second direction to provide a third inset gap between the third portion of the second insulative material and the narrow fin region and a fourth inset gap between the fourth portion of the second insulative material and the narrow fin region.

16. The method of claim 14 , wherein the selectively etching the semiconductor panel causes the first post region to include a first side surface defining the first inset gap and the second post region to include a second side surface defining the second inset gap; and

wherein the method further comprises:

forming gate dielectric material on top and side surfaces of the narrow fin region, the first side surface of the first post region and the second side surface of the second post region with leaving respective parts of the first and second inset gaps; and

forming gate material over the gate dielectric material to fill the first and second trenches and the respective parts of the first and second inset gaps.

17. The method of claim 13 , wherein the first and second post regions are elongated structures comprising upper terminal ends elevational above upper terminal ends of the fin region.

18. The method of claim 13 , wherein the first and second trenches expose an upper surface of the fin region comprising an H configuration.

19. The method of claim 13 , wherein the first and second insulative materials comprise sides that extend to upper terminal ends that are coplanar and against entire sides and upper terminal ends of the semiconductor panel.

20. The method of claim 13 , wherein the first and second post regions comprises a pair of separate and discrete structures that extend elevational above the fin region and are devoid of the material from the semiconductor panel between the pair of the separate and discrete structures.

21. The method of claim 13 , wherein linear middle portion of the fin region and the two end portions of the fin region are exposed between the first and second insulative materials, and exposed between the first and second post regions.