IP Library Granted Patent US 10,127,994
Granted Patent B1
US 10,127,994 · App. 15/789,167 · Granted Nov 13, 2018

Systems and methods for threshold voltage modification and detection

Inventors: Daniel B. Penney (Wylie, TX); William C. Waldrop (Allen, TX)
Assignee: Micron Technology, Inc.
G11C17/18G11C17/16H04L9/0816G11C17/08
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Quick Facts
Patent No.
US 10,127,994
App. No.
15/789,167
Granted
Nov 13, 2018
Kind
B1
Abstract

A memory device includes a memory array of a set of memory cells. Each memory cell of the set of memory cells includes at least one transistor and at least one capacitor. The memory array includes at least one programmed memory cell. The programmed memory cell is selectively programmed by applying hot-carrier injection (HCI) to a transistor of the programmed memory cell. The programmed memory cell may provide an indication of pattern data that may be used to facilitate functionality such as data encryption, data decryption, implementation of a particular memory device operation mode, and/or machine-implemented instructions.

Claims (26)

1. One-time programming (OTP) injection circuitry, comprising circuitry configured to:

program at least one memory cell of a memory array by applying hot-carrier injection (HCI) to a transistor of the at least one memory cell; and

perform an HCI application cycle, comprising:

initializing the at least one memory cell for programming;

then raising a plate voltage of the at least one memory cell;

then lowering a selected digit of the memory cell to introduce a strong HCI; and

then lowering the plate voltage of the at least one memory cell.

2. The OTP injection circuitry of claim 1 , comprising circuitry configured to:

determine a desired pattern to introduce into the memory array;

identify memory cells of the memory array to be programmed to form the desired pattern; and

applying the HCI to each of the identified memory cells of the memory area to be programmed.

3. The OTP injection circuitry of claim 1 , comprising circuitry configured to:

repetitively perform the HCI application cycle until a target threshold voltage (Vth) change is reached.

4. The OTP injection circuitry of claim 3 , wherein the target threshold voltage (Vth) change comprises a range of 200-300 mV.

5. A method, comprising:

identifying one or more programmed memory cells of a memory array, wherein the one or more programmed memory cells are programmed by applying hot-carrier injection (HCI) to a transistor of the one or more programmed memory cells;

based upon the one or more programmed memory cells, identifying programmed pattern data; and

implementing one or more data processing functions based upon the programmed pattern data;

wherein identifying the one or more programmed memory cells, comprises:

initializing the one or more programmed memory cells, by writing a “1” to the one or more programmed memory cells and a reference memory cell, a reference digit, or both, when a word line voltage of the one or more programmed memory cells is sufficient to change a capacitor voltage of the one or more programmed memory cells and a capacitor voltage of the reference memory cell, the reference digit, or both;

then modifying the word line voltage to a voltage sufficient to change a capacitor voltage of the reference memory cell, the reference digit, or both, but not the capacitor voltage of the one or more programmed memory cells, when a “0” is written to the one or more programmed memory cells and the reference memory cell, the reference digit or both;

then writing the “0” to the one or more programmed memory cells and the reference memory cell, the reference digit, or both;

then comparing the capacitor voltage of the one or more programmed memory cells with the capacitor voltage of the reference memory cell, the reference digit, or both; and

when the capacitor voltage of the programmed memory cell differs from the capacitor voltage of the reference memory cell, the reference digit, or both, determining that the one or more programmed memory cells are programmed.

6. The method of claim 5 , comprising:

based upon the programmed pattern data: implementing decryption, implementing encryption, implementing a boot-up routine, implementing a particular memory device operating mode, or any combination thereof.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 20, 2017
From: PENNEY, DANIEL B.; WALDROP, WILLIAM C.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044255/0099 →