IP Library Granted Patent US 10,504,576
Granted Patent B2
US 10,504,576 · App. 15/846,765 · Granted Dec 10, 2019

Current separation for memory sensing

Inventor: Daniele Vimercati (El Dorado Hills, CA)
Assignee: Micron Technology, Inc.
G11C11/2273G11C11/221G11C11/2275G11C11/2293G11C11/2297G11C13/004G11C11/5657
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Quick Facts
Patent No.
US 10,504,576
App. No.
15/846,765
Granted
Dec 10, 2019
Kind
B2
Abstract

The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

Claims (89)

1. A method of operating memory, comprising:

pre-charging a data line to which a memory cell having a ferroelectric material is coupled before applying a sensing voltage to the memory cell;

applying a sensing voltage to the memory cell; and

determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell by continuing to pre-charge the data line to which the memory cell is coupled while the sensing voltage is being applied to the memory cell until a particular reference time, wherein:

the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell; and

the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

2. The method of claim 1 wherein the particular reference time is based on a time at which a polarization state of the ferroelectric material of the memory cell changes from the first polarization state to the second polarization state.

3. The method of claim 1 , wherein:

separating the first current output by the memory cell while the sensing voltage is being applied to the memory cell and the second current output by the memory cell while the sensing voltage is being applied to the memory cell includes separating charge discharged by the memory cell corresponding to the first current output by the memory cell and charge discharged by the memory cell corresponding to the second current output by the memory cell; and

the data state of the memory cell is determined using only the charge discharged by the memory cell corresponding to the second current output by the memory cell.

4. The method of claim 3 , wherein the method includes determining the data state of the memory cell based on a comparison of:

a voltage amount associated with the charge discharged by the memory cell corresponding to the second current output by the memory cell; and

a reference voltage.

5. An apparatus comprising:

a memory cell having a ferroelectric material; and

circuitry configured to:

apply a sensing voltage to the memory cell; and

determine a data state of the memory cell by separating a current output by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and a current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time, wherein the particular reference time is based on a time at which a change of a polarization state of the ferroelectric material of the memory cell occurs.

6. The apparatus of claim 5 , wherein the circuitry is configured to:

pre-charge a data line to which the memory cell is coupled before applying the sensing voltage to the memory cell; and

separate the current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time by continuing to pre-charge the data line to which the memory cell is coupled while the sensing voltage is being applied to the memory cell until the particular reference time.

7. The apparatus of claim 5 , wherein:

the circuitry includes a capacitor coupled to the memory cell and configured to store only charge discharged by the memory cell corresponding to the second current output by the memory cell while the sensing voltage is being applied to the memory cell; and

the circuitry is configured to determine the data state of the memory cell based on the charge stored by the capacitor.

8. The apparatus of claim 7 , wherein the circuitry is configured to determine the data state of the memory cell based on a comparison of:

a voltage amount associated with the charge stored by the capacitor; and

a reference voltage.

9. The apparatus of claim 8 , wherein:

the data state of the memory cell is a first data state upon the comparison indicating the voltage amount associated with the charge stored by the capacitor is less than the reference voltage; and

the data state of the memory cell is a second data state upon the comparison indicating the voltage amount associated with the charge stored by the capacitor is greater than the reference voltage.

10. The apparatus of claim 6 , wherein the circuitry includes a cascode configured to couple the capacitor to the memory cell.

11. The apparatus of claim 6 , wherein charge discharged by the memory cell corresponding to the first current output by the memory cell while the sensing voltage is being applied to the memory cell is not stored by the capacitor.

12. A method of operating memory, comprising:

applying a sensing voltage to a memory cell having a ferroelectric material;

separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein:

the first current corresponds to a first polarization state of the ferroelectric material of the memory cell; and

the second current corresponds a second polarization state of the ferroelectric material of the memory cell wherein the first polarization state is different from the second polarization state; and

determining a data state of the memory cell using only the second current output by the memory cell.

13. The method of claim 12 , wherein determining the data state of the memory cell using only the second current output by the memory cell includes determining the data state of the memory cell without using the first current output by the memory cell.

14. The method of claim 12 , wherein the method includes determining the data state of the memory cell based on an amount of time for which the second current is output by the memory cell.

15. An apparatus comprising:

a memory cell having a ferroelectric material; and

circuitry configured to:

apply a sensing voltage to the memory cell;

separate a current output by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and a current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time, wherein the particular reference time is based on a time at which a change of a polarization state of the ferroelectric material of the memory cell occurs; and

determine a data state of the memory cell using only the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

16. The apparatus of claim 15 , wherein the circuitry includes a switch configured to separate the current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

17. The apparatus of claim 15 , wherein the circuitry includes a transistor configured to separate the current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

18. The apparatus of claim 17 , wherein the circuitry includes a resistor in parallel with the transistor.

19. The apparatus of claim 17 , wherein the transistor is a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET).

20. A method of operating memory, comprising:

applying a sensing voltage to a memory cell having a ferroelectric material;

pre-charging a data line to which the memory cell is coupled before applying the sensing voltage to the memory cell;

continuing to pre-charge the data line to which the memory cell is coupled while the sensing voltage is being applied to the memory cell until a particular reference time, wherein the particular reference time is based on a time at which a change of a polarization state of the ferroelectric material of the memory cell occurs; and

determining a data state of the memory cell by separating a current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and a current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

21. The method of claim 20 , wherein the method includes separating the current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time by:

enabling a switch coupled to the memory cell before the particular reference time; and

disabling the switch after the particular reference time.

22. The method of claim 20 , wherein the method includes separating the current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time by:

enabling a transistor coupled to the memory cell before the particular reference time; and

disabling the transistor after the particular reference time.

23. The method of claim 20 , wherein the particular reference time is approximately ten nanoseconds after the sensing voltage has begun to be applied to the memory cell.

24. An apparatus, comprising:

a memory cell having a ferroelectric material; and

circuitry configured to:

apply a sensing voltage to the memory cell;

pre-charge a data line to which the memory cell is coupled before applying the sensing voltage to the memory cell;

continue to pre-charge the data line to which the memory cell is coupled while the sensing voltage is being applied to the memory cell until a particular reference time;

separate a current output by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time and a current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time; and

determine a data state of the memory cell using only the current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

25. The apparatus of claim 24 , wherein the circuitry includes a cascode coupled to the memory cell and configured to apply the sensing voltage to the memory cell.

26. The apparatus of claim 24 , wherein the circuitry includes a latch configured to determine the data state of the memory cell.

27. The apparatus of claim 24 , wherein the sensing voltage is approximately 1.6 Volts.

28. The apparatus of claim 24 , wherein the ferroelectric material is an oxide material.

29. A method of operating memory, comprising:

applying a sensing voltage to a memory cell having a ferroelectric material; and

determining a data state of the memory cell by:

separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, including separating charge discharged by the memory cell corresponding to the first current output by the memory cell and charge discharged by the memory cell corresponding to the second current output by the memory cell, wherein:

the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell;

the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell wherein the first polarization state is different from the second polarization state; and

using only the charge discharged by the memory cell corresponding to the second current output by the memory cell.

30. An apparatus comprising:

a memory cell having a ferroelectric material; and

circuitry configured to:

apply a sensing voltage to the memory cell; and

determine a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and a second current output by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time;

wherein:

the circuitry includes a capacitor coupled to the memory cell and configured to store only charge discharged by the memory cell corresponding to the second current output by the memory cell while the sensing voltage is being applied to the memory cell; and

the circuitry is configured to determine the data state of the memory cell based on the charge stored by the capacitor.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2018
From: VIMERCATI, DANIELE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044625/0973 →
Continuity (1)
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