IP Library Granted Patent US 10,121,799
Granted Patent B2
US 10,121,799 · App. 15/851,532 · Granted Nov 6, 2018

Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials

Inventors: Fei Wang (Boise, ID); Tom J. John (Boise, ID); Kunal Shrotri (Boise, ID); Anish A. Khandekar (Boise, ID); Aaron R. Wilson (Boise, ID); John D. Hopkins (Meridian, ID); Derek F. Lundberg (Kuna, ID)
Assignee: Micron Technology, Inc.
H01L27/11582H01L21/0332H01L21/0337H01L21/31116H01L21/31144H01L27/11556H01L29/7883
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Quick Facts
Patent No.
US 10,121,799
App. No.
15/851,532
Granted
Nov 6, 2018
Kind
B2
Abstract

A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H 3 PO 4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H 3 PO 4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Claims (16)

1. An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:

vertically-alternating tiers of insulative material and control gate material;

a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;

tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and

silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion comprising boron, the encircling silicon nitride-comprising material comprising an elevationally-innermost portion having less boron content, if any, than the elevationally-outermost portion.

2. The string of memory cells of claim 1 wherein said boron content is constant elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

3. The string of memory cells of claim 1 wherein boron is in the elevationally-innermost portion, said boron content being variable elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

4. The string of memory cells of claim 1 wherein the elevationally-outermost portion has 1 to 20 atomic percent boron.

5. The string of memory cells of claim 1 wherein the elevationally-innermost portion has zero to 0.001 atomic percent boron.

6. The string of memory cells of claim 1 wherein difference in said boron content is along a stepped gradient.

7. The string of memory cells of claim 6 comprising three steps in the stepped gradient between an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.

8. The string of memory cells of claim 1 wherein difference in said boron content is along a linear gradient.

9. The string of memory cells of claim 8 wherein the linear gradient is straight.

10. The string of memory cells of claim 9 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.

11. The string of memory cells of claim 8 wherein the linear gradient is curved.

12. The string of memory cells of claim 11 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
Continuity (2)
Division 15293133 · Oct 13, 2016
Related Publication 20180114795A1 · Apr 26, 2018