IP Library Granted Patent US 10,366,763
Granted Patent B2
US 10,366,763 · App. 15/799,616 · Granted Jul 30, 2019

Block read count voltage adjustment

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,366,763
App. No.
15/799,616
Granted
Jul 30, 2019
Kind
B2
Abstract

Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

Claims (34)

1. A NAND memory device comprising:

a NAND memory array including a first pool of memory;

a controller executing instructions and performing operations comprising:

receiving a command from a host to read a value of at least one cell from the first pool of memory;

determining a read voltage to apply to the at least one cell by adding a first offset value to a base read voltage, the first offset value calculated as a stepwise function of a count of a number of previous reads during a period of time to a group of cells, the group of cells including the at least one cell; and

applying the read voltage to the at least one cell.

2. The NAND memory device of claim 1 , wherein the read voltage is for a first page, the first page including the at least one cell, and wherein the operations of applying the read voltage to the at least one cell includes applying the read voltage to the at least one cell to read a first value of the at least one cell.

3. The NAND memory device of claim 2 , wherein the operations further comprise:

determining second and third read voltages to apply to the at least one cell based upon the count; and

applying the second and third read voltages to the at least one cell to read second and third values of the at least one cell.

4. The NAND memory device of claim 3 wherein determining the second read voltage comprises adding a second offset value to a second base read voltage, and wherein determining the third read voltage comprises adding a third offset value to a third base read voltage, wherein at least two of the first offset value, the second offset value, and the third offset value are different values.

5. The NAND memory device of claim 1 , wherein the operations of determining the read voltage to apply to the at least one cell comprises adjusting the determined read voltage based upon a wear indicator.

6. The NAND memory device of claim 1 , wherein the operations further comprise reading the value of the at least one cell and sending the value to the host.

7. The NAND memory device of claim 1 , wherein the NAND memory device is a three-dimensional NAND device.

8. A method performed by a NAND memory device, the method comprising:

receiving a command from a host to read a value of at least one cell from a first pool of memory of the NAND memory device;

determining a read voltage to apply to the at least one cell by adding a first offset value to a base read voltage, the first offset value calculated as a stepwise function of a count of a number of previous reads during a period of time to a group of cells, the group of cells including the at least one cell; and

applying the read voltage to the at least one cell.

9. The method of claim 8 , wherein the read voltage is for a first page, the first page including the at least one cell, and wherein applying the read voltage to the at least one cell includes applying the read voltage to the at least one cell to read a first value of the at least one cell.

10. The method of claim 9 , wherein the method further comprises:

determining second and third read voltages to apply to the at least one cell based upon the count; and

applying the second and third read voltages to the at least one cell to read second third values of the at least one cell.

11. The method of claim 10 , wherein determining the second read voltage comprises adding a second offset value to a second base read voltage, and wherein determining the third read voltage comprises adding a third offset value to a third base read voltage, wherein at least two of the first offset value, the second offset value, and the third offset value are different values.

12. A machine-readable medium comprising instructions, which performed by a machine, causes the machine to perform operations comprising:

receiving a command from a host to read a value of at least one cell from a first pool of memory cells in a NAND memory device;

determining a read voltage to apply to the at least one cell by adding a first offset value to a base read voltage, the first offset value calculated as a stepwise function of a count of a number of previous reads during a period of time to a group of cells, the group of cells including the at least one cell; and

applying the read voltage to the at least one cell.

13. The machine-readable medium of claim 12 , wherein the read voltage is for a first page, the first page including the at least one cell, and wherein the operations of applying the read voltage to the at least one cell includes applying the read voltage to the at least one cell to read a first value of the at least one cell.

14. The machine-readable medium of claim 13 , wherein the operations further comprise:

determining second and third read voltages to apply to the at least one cell based upon the count; and

applying the second and third read voltages to the at least one cell to read second and third values of the at least one cell.

15. The machine-readable medium of claim 14 , wherein the operations of determining the second read voltage comprises adding a second offset value to a second base read voltage, wherein the operations of determining the third read voltage comprises adding a third offset value to a third base read voltage, wherein at least two of the first offset value, the second offset value, and the third offset value are different values.

16. The machine-readable medium of claim 12 , wherein the operations of determining the read voltage to apply to the at least one cell comprises adjusting the determined read voltage based upon a wear indicator.

17. The machine-readable medium of claim 12 , wherein the operations further comprise reading the value of the at least one cell and sending the value to the host.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2018
From: SINGIDI, HARISH REDDY; MUCHHERLA, KISHORE KUMAR; ALSASUA, GIANNI STEPHEN; MALSHE, ASHUTOSH; RATNAM, SAMPATH; BESINGA, GARY F; MILLER, MICHAEL G
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047426/0765 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →