Three-dimensional memory apparatuses and methods of use
View Patent ↗A three dimensional (3D) memory array is disclosed. The 3D memory array may include an electrode plane and a memory material disposed through and coupled to the electrode plane. A memory cell included in the memory material is aligned in a same plane as the electrode plane, and the memory cell is configured to exhibit a first threshold voltage representative of a first logic state and a second threshold voltage representative of a second logic state. A conductive pillar is disposed through and coupled to the memory cell, wherein the conductive pillar and electrode plane are configured to provide a voltage across the memory cell to write a logic state to the memory cell. Methods to operate and to form the 3D memory array are disclosed.
1. A method comprising:
receiving a first address corresponding to a conductive pillar in an array of conductive pillars;
receiving a second address corresponding to an electrode plane in a stack of electrode planes;
coupling the conductive pillar to a first voltage;
coupling the electrode plane to a second voltage; and
biasing a memory cell coupled between the conductive pillar and the electrode plane by a difference between the first voltage and the second voltage,
wherein the memory cell is configured to act as a selector device and a memory element.
2. The method of claim 1 , further comprising:
coupling conductive pillars in the array of conductive pillars that do not correspond to the first address to a common voltage; and
coupling electrode planes in the stack of electrode planes that do not correspond to the second address to the common voltage.
3. The method of claim 1 , wherein:
the first voltage is greater than the second voltage, and
responsive to the biasing, a first logic state is written to the memory cell, or wherein:
the first voltage is less than the second voltage; and
responsive to the biasing, a second logic state is mitten to the memory cell.
4. The method of claim 3 , wherein the first logic state corresponds to a first threshold voltage of the memory cell, and
wherein the second logic state corresponds to a second threshold voltage of the memory cell.
5. The method of claim 4 , further comprising:
coupling the conductive pillar to a third voltage;
coupling the electrode plane to a fourth voltage;
biasing the memory cell coupled between the conductive pillar and the electrode plane by a difference between the third voltage and the fourth voltage, wherein the third voltage is greater than the fourth voltage; and
responsive to the biasing, determining a logic state of the memory cell.
6. The method of claim 1 , wherein the first voltage is greater than the second voltage and responsive to the biasing, a first logic state is written to the memory cell.
7. The method of claim 1 , wherein the first voltage is less than the second voltage and responsive to the biasing, a second logic state is written to the memory cell.
8. The method of claim 1 , wherein biasing of the memory cell comprises:
to write to the memory cell with a positive polarity at voltage +V P , biasing the conductive pillar of the memory cell to voltage +V P /2; and
biasing the electrode plane of the memory cell to voltage −V P /2.
9. The method of claim 1 , wherein biasing of the memory cell comprises:
to write to the memory cell with a negative polarity at voltage −V P , biasing the conductive pillar of the memory cell to voltage −V P /2; and
biasing the electrode plane of the memory cell to voltage +V P /2.
10. The method of claim 1 , wherein the first address is received at a row address decoder and a column address decoder and the second address is received at an electrode plane address decoder.
11. A method comprising:
applying a write voltage of a first polarity across a memory cell coupled between a conductive pillar and an electrode plane by a difference between the conductive pillar and the electrode plane; and
applying a read voltage of a second polarity to the memory cell,
wherein the memory cell is configured to act as a selector device and a memory element.
12. The method of claim 11 , wherein the first polarity is applied when the memory cell is written, and the second polarity is the same as the first polarity.
13. The method of claim 12 , wherein the polarity in which the read voltage is read is a forward polarity.
14. The method of claim 11 , wherein the read voltage is applied in a same polarity each time the read voltage is read.
15. The method of claim 14 , wherein the polarity in which the read voltage is read is a forward polarity.
16. An apparatus comprising:
a conductive pillar included in a memory column and configured to be coupled to a first voltage;
an electrode plane configured to be coupled to a second voltage; and
a memory cell coupled between the conductive pillar and the electrode plane and configured to be biased corresponding to a difference between the first voltage and the second voltage,
wherein the memory cell is configured to act as a selector device and a memory element responsive, at least in part, to a polarity of a voltage applied across the memory cell as the difference between the first voltage and the second voltage.
17. The apparatus of claim 16 , wherein the first voltage is greater than the second voltage, and
wherein, responsive to the biasing, a first logic state is written to the memory cell.
18. The apparatus of claim 16 , wherein the first voltage is less than the second voltage, and
wherein, responsive to the biasing, a second logic state is written to the memory cell.
19. The apparatus of claim 16 , wherein a read voltage further is applied to the memory cell in a same polarity as when the memory cell was written.
20. The apparatus of claim 19 , wherein the polarity in which the read voltage is read is a forward polarity.