Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
1. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause e memory device to perform a memory operation, the memory device including:
first memory cells located in a first device level of a memory device;
second memory cells located in a second device level of the memory device;
a first control gate formed in the first device level, the first control gate to control access to the first memory cells, the first memory cells including a first memory cell having a first memory element formed in a cavity of the first control gate;
a second control gate formed in the second device level, the second control gate to control access to the second memory cells, the second memory cells including a second memory cell having a second memory element formed in a cavity of the second control gate;
a dielectric electrically separating the first memory element from the second memory element; and
a channel extending between the first and second memory cells.
2. The system of claim 1 , wherein the additional device is external to the memory device.
3. The system of claim 1 , wherein the additional device includes a processor.
4. The system of claim 1 , herein the additional device includes a memory controller.
5. The system of claim 1 , wherein the additional device is configured to control signals provided to the memory device to cause the memory device to perform the memory operation based on signals.
6. The system of claim 1 , wherein the additional device is configured to control signals provided to conductive lines coupled to the memory device to cause the memory device to perform the memory operation based on signals.
7. The system of claim 1 , wherein each of the first and second memory elements is polysilicon.
8. The system of claim 1 , wherein each of the first and second memory elements is dielectric material.
9. The system of claim 1 , further comprising:
a substrate; and
a data line configured to be coupled to the channel, wherein the data line is located between the second conductive material and the substrate.
10. The system of claim 1 , further comprising:
a substrate; and
a data line configured to be coupled to the channel, wherein the first and second memory elements are located between the data line and the substrate.
11. The system of claim 1 , further comprising:
multiple dielectric materials between the first memory element and the first control gate; and
multiple dielectric materials between the second memory element and the second control gate.
12. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a first non-volatile memory cell including a first memory element, the first memory element having a ring shape;
a second non-volatile memory cell including a second memory element, the second memory element having a ring shape;
a dielectric electrically separating the first memory element from the second memory element; and
a material to form a conductive path through the first and second memory cells.
13. The system of claim 12 , further comprising:
a first dielectric structure between the first memory element and the first control gate; and
a second dielectric structure between the second memory element and the second control gate, the each of the first and second dielectric structures including silicon nitride between a first silicon oxide and a second silicon oxide.
14. The system of claim 12 , further comprising a common source formed over a substrate of the memory device, the common is between the substrate and the first and second memory cells.
15. The system of claim 12 , further comprising a common source formed over a substrate of the memory device, the first and second memory cells are between the common source and the substrate.
16. The system of claim 12 , wherein the material to form the conductive path includes polysilicon.
17. The system of claim 12 , wherein h of the first and second memory elements is silicon nitride.
18. A system comprising:
a memory device; and
an additional device coupled to the memory device to cause the memory device to perform a memory operation, the memory device including:
a first conductive material located in a first device level of a memory device, the first conductive material including a first cavity, the first cavity having a first sidewall;
a second conductive material located in a second device level of the memory device, the second conductive material including a second cavity, the second cavity having a second sidewall;
a first dielectric formed on the first sidewall;
a second dielectric formed on the second sidewall;
a first memory element of a first memory cell, the first memory element located in the first cavity and electrically isolated from the first conductive material by the first dielectric;
a second memory element of a second memory cell, the second memory element located in the second cavity and electrically isolated from the second conductive material by the second dielectric;
a third dielectric electrically separating the first memory element from e second memory element; and
a material to form a conductive path through the first and second memory cells.
19. The system of claim 18 , wherein each of the first and second dielectrics includes silicon nitride.
20. The system of claim 18 , wherein the additional device is configured to control signals provided to solder balls of the memory device to cause the memory device to perform the memory operation based on signals.