Granted Patent B2

US 12,426,262 · App. 18/108,970 · Granted Sep 23, 2025

Inventors: Sanh D. Tang (Boise, ID); John K. Zahurak (Eagle, ID)

Assignee: Micron Technology, Inc.

H10B41/27H10B41/30H10B41/35H10B43/20H10B43/27H10D30/689H10D30/69H10D62/40H10D62/834H10D64/035H10D64/037H10D64/665H10D64/667H10D30/693

Abstract

Claims (21)

1. An apparatus, comprising:

a silicon channel material forming a channel for multiple memory cells in a string of NAND memory cells;

a first charge storage structure of a first memory cell in the string of NAND memory cells, the first charge storage structure at least partially surrounding the silicon channel material in a first tier;

a second charge storage structure of a second memory cell of the string of NAND memory cells, the second charge storage structure surrounding the silicon channel material in a second tier;

a first dielectric structure having a first surface in contact with the first charge storage structure and the second charge storage structure, and having an opposing surface in contact with the silicon channel material;

wherein the first and second memory cells comprise at least a portion of first and second word lines, the first and second word lines each having a respective planar vertical end surface facing the respective first and second charge storage structures;

a second dielectric structure extending horizontally between the first and second word lines, wherein each of the first and second charge storage structures contacts the horizontally extending second dielectric structure;

a third dielectric structure extending between the first word line and the first charge storage structure, wherein a vertical dimension of the third dielectric structure is greater than a vertical dimension of the first word line; and

a fourth dielectric structure extending between the second word line and the second charge storage structure, wherein a vertical dimension of the fourth dielectric structure is greater than a vertical dimension of the second word line.

2. The apparatus of claim 1 , wherein the first dielectric structure, the third dielectric structure, and the fourth dielectric structure each comprise an oxide material.

3. The apparatus of claim 1 , wherein the third dielectric structure and the fourth dielectric structure each include a material selected from zirconium oxide, hafnium oxide, aluminum oxide, and titanium oxide.

4. The apparatus of claim 1 , wherein each of the first and second charge storage structures comprises a first respective planar vertical surface facing the respective first or second word line.

5. The apparatus of claim 4 , wherein each of the first and second charge storage structures further comprises an opposing second respective planar vertical surface contacting the first dielectric structure.

6. The apparatus of claim 1 , wherein each of the first and second charge storage structures comprises a respective planar vertical surface contacting the first dielectric structure.

7. The apparatus of claim 1 , wherein each of the first and second charge storage structures extends completely around the silicon channel material.

8. The apparatus of claim 1 , wherein the silicon channel material forms a U-shape.

9. The apparatus of claim 1 , wherein the first charge storage structure comprises a ring of doped polysilicon around the silicon channel material at the first tier, and wherein the second charge storage structure comprises a ring of doped polysilicon around the silicon channel material at the second tier.

10. The apparatus of claim 9 , wherein:

the first word line and the second word line each comprise a metal; and

wherein each of the first and second word lines surrounds the respective ring of doped polysilicon.

11. The apparatus of claim 1 , wherein the first and second charge storage structures each comprise polysilicon.

Continuity (6)

References Cited (167)