Vertical-type non-volatile memory devices and methods of manufacturing the same
In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.
1. A method of fabricating a semiconductor device comprising:
providing a substrate of single-crystal semiconductor material extending in a horizontal direction;
providing a plurality of interlayer dielectric layers on the substrate;
providing a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;
providing a vertical channel of semiconductor material extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns;
providing a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel; and,
wherein providing each of the plurality of interlayer dielectric layers comprises providing a multiple-layered structure comprising a lower insulating layer, an intermediate insulating layer and an upper insulating layer, the lower and upper insulating layers comprising a material that has etch selectivity relative to the intermediate insulating layer.
2. The method of claim 1 further comprising providing a charge trapping layer between each corresponding gate pattern and gate insulating layer, the charge trapping layer including:
a first portion extending in the vertical direction between the gate pattern and the gate insulating layer;
a second portion extending in the horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer; and
a third portion extending in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.
3. The method of claim 2 wherein the charge trapping layer comprises a floating gate comprising a conducting or a semi-conducting material.
4. The method of claim 1 wherein providing the gate insulating layer comprises a providing a thermal oxide layer.
5. The method of claim 1 wherein:
an upper-most gate pattern of the plurality of gate patterns comprises an upper select gate of an upper select transistor;
a lower-most gate pattern of the plurality of gate patterns comprises a lower select gate of a lower select transistor;
remaining gate patterns of the plurality of gate patterns between the upper select gate and the lower select gate comprise control gates of memory cell transistors of a common string of the semiconductor device;
control gates of memory cell transistors sharing a same layer of the device arranged in a first horizontal direction of the semiconductor device are connected to provide word lines of the semiconductor device,
and further comprising:
coupling memory cell transistors of a common string of the semiconductor device together in series; and
connecting upper portions of vertical channels arranged in a second horizontal direction of the semiconductor device to provide bit lines of the semiconductor device, wherein the semiconductor device comprises a semiconductor memory device.
6. A method of fabricating a semiconductor device comprising:
providing a substrate extending in a horizontal direction;
providing a plurality of interlayer dielectric layers on the substrate;
providing a plurality of gate patterns, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer;
providing a vertical channel extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns;
providing a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel; and
providing a charge trapping layer between each corresponding gate pattern and gate insulating layer, the charge trapping layer including: a first portion extending in the vertical direction between the gate pattern and the gate insulating layer; a second portion extending in the horizontal direction between the gate pattern and the neighboring upper interlayer dielectric layer; and a third portion extending in the horizontal direction between the gate pattern and the neighboring lower interlayer dielectric layer.
7. The method of claim 6 wherein providing the substrate comprises providing a substrate comprising single-crystal semiconductor material, and wherein providing the vertical channel comprises providing a vertical channel comprising single-crystal semiconductor material.
8. The method of claim 7 wherein providing the vertical channel comprises processing of a laser-induced epitaxial growth (LEG).
9. The method of claim 6 wherein the charge trapping layer comprises a floating gate comprising a conducting or a semi-conducting material.
10. The method of claim 6 wherein providing the gate insulating layer comprises providing a thermal oxide layer.
11. The method of claim 6 wherein:
an upper-most gate pattern of the plurality of gate patterns comprises an upper select gate of an upper select transistor;
a lower-most gate pattern of the plurality of gate patterns comprises a lower select gate of a lower select transistor;
remaining gate patterns of the plurality of gate patterns between the upper select gate and the lower select gate comprise control gates of memory cell transistors of a common string of the semiconductor device;
control gates of memory cell transistors sharing a same layer of the device arranged in a first horizontal direction of the semiconductor device are connected to provide word lines of the semiconductor device,
and further comprising:
coupling memory cell transistors of a common string of the semiconductor device together in series; and
connecting upper portions of vertical channels arranged in a second horizontal direction of the semiconductor device to provide bit lines of the semiconductor device, wherein the semiconductor device comprises a non-volatile semiconductor memory device.
12. The method of claim 6 wherein providing each of the plurality of interlayer dielectric layers comprises providing a multiple-layered structure comprising a lower insulating layer, an intermediate insulating layer and an upper insulating layer, the lower and upper insulating layers comprising a material that has etch selectivity relative to the intermediate insulating layer.
13. The method of claim 6 further comprising doping the vertical channel, wherein doping the vertical channel comprises plasma doping (PLAD).