Three dimensional memory and methods of forming the same
Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.
1. An apparatus comprising:
conductive regions formed over a substrate;
memory cell strings, each of the memory cell strings formed over a respective conductive region of the conductive regions;
a first control gate formed in a first device level, the memory cell strings including a memory cell string, the memory cell string including a first memory cell having a memory element formed in a cavity of the first control gate;
a second control gate formed in a second device level, the memory cell string including a second memory cell having a memory element formed in a cavity of the second control gate; and
a polysilicon material extending between the first memory cell and the second memory cell and coupled to a conductive region of the conductive regions.
2. The apparatus of claim 1 , further comprising:
a first conductive region located on a first side of the conductive region and separated from the conductive region by a first dielectric material; and
a second conductive region located on a second side opposite from the first side of the conductive region and separated from the conductive region by a second dielectric material.
3. The apparatus of claim 2 , wherein the first conductive region is coupled to the second conductive region.
4. The apparatus of claim 2 , wherein each of the first and second conductive regions comprises polysilicon.
5. The apparatus of claim 2 , wherein each of the first and second conductive regions comprises metal.
6. The apparatus of claim 1 , further comprising a data line coupled to the polysilicon material, wherein the data line is located between the substrate and the first and second memory cells.
7. The apparatus of claim 1 , further comprising a data line coupled to the polysilicon material, wherein the first and second memory cells are located between the data line and the substrate.
8. The apparatus of claim 1 , wherein the memory element comprises polysilicon.
9. The apparatus of claim 1 , wherein the memory element comprises a dielectric material.
10. An apparatus comprising:
a first conductive region and a second conductive region formed over a substrate;
a first data line coupled to the first and second conductive regions, the first data line located between the first and second conductive regions and the substrate;
a third conductive region and a fourth conductive regions formed over the substrate;
a second data line coupled to the third and fourth conductive regions, the second data line located between the third and fourth conductive regions and the substrate;
a first memory cell string formed over the first conductive region;
a second memory cell string formed over the second conductive region;
a third memory cell string formed over the third conductive region;
a fourth memory cell string formed over the fourth conductive region;
a first control gate formed in a first device level;
a second control gate formed in a second device level, wherein,
the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate;
the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate;
the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate; and
the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate.
11. The apparatus of claim 10 , further comprising:
a first polysilicon material coupled to the first conductive region and extending between the first and second memory cells;
a second polysilicon material coupled to the second conductive region and extending between the third and fourth memory cells;
a third polysilicon material coupled to the third conductive region and extending between the fifth and sixth memory cells; and
a fourth polysilicon material coupled to the fourth conductive region and extending between the seventh and eighth memory cells.
12. The apparatus of claim 10 , further comprising a first conductive gate including a first segment and a second segment coupled to the first segment, wherein:
the first segment is located on a first side of each of the first and third conductive regions and separated from the first and third conductive regions by a first dielectric material; and
the second segment is located on a second side of each of the first and third conductive regions and separated from the first and third conductive regions by a second dielectric material.
13. The apparatus of claim 12 , further comprising a second conductive gate including a third a segment and a fourth segment coupled to the third segment, wherein:
the third segment is located on a first side of each of the second and fourth conductive regions and separated from the second and fourth conductive regions by a third dielectric material; and
the fourth segment is located on a second side of each of the second and fourth conductive regions and separated from the second and fourth conductive regions by a fourth dielectric material.
14. The apparatus of claim 13 , wherein each of the first and second conductive gates comprises polysilicon.
15. The apparatus of claim 13 , wherein each of the first and second conductive gates comprises metal.
16. The apparatus of claim 10 , wherein the memory element of each of the first, second, third, and fourth memory cells comprises one of polysilicon and a dielectric material.
17. An apparatus comprising:
a first conductive region and a second conductive region formed over a substrate;
a third conductive region and a fourth conductive regions formed over the substrate;
a region including a conductive material, the region coupled to the first, second, third, and fourth conductive regions, the region located between substrate and the first, second, third, and fourth conductive regions;
a first memory cell string formed over the first conductive region;
a second memory cell string formed over the second conductive region;
a third memory cell string formed over the third conductive region;
a fourth memory cell string formed over the fourth conductive region;
a first data line coupled to the first and second memory cell strings, the first and second memory cell strings located between the first data line and the substrate;
a second data line coupled to the third and fourth memory cell strings, the third and fourth memory cell strings located between the second data line and the substrate;
a first control gate formed in a first device level;
a second control gate formed in a second device level, wherein,
the first memory cell string includes a first memory cell having a memory element formed in a first cavity of the first control gate, and a second memory cell having a memory element formed in a first cavity of the second control gate;
the second memory cell string includes a third memory cell having a memory element formed in a second cavity of the first control gate, and a fourth memory cell having a memory element formed in a second cavity of the second control gate;
the third memory cell string includes a fifth memory cell having a memory element formed in a third cavity of the first control gate, and a sixth memory cell having a memory element formed in a third cavity of the second control gate; and
the fourth memory cell string includes a seventh memory cell having a memory element formed in a fourth cavity of the first control gate, and an eighth memory cell having a memory element formed in a fourth cavity of the second control gate.
18. The apparatus of claim 17 , wherein the memory element of each of the first, second, third, and fourth memory cells comprises polysilicon.
19. The apparatus of claim 17 , wherein the memory element of each of the first, second, third, and fourth memory cells comprises a silicon nitride.
20. The apparatus of claim 17 , further comprising:
a first polysilicon material coupled to the first conductive region and extending between the first and second memory cells;
a second polysilicon material coupled to the second conductive region and extending between the third and fourth memory cells;
a third polysilicon material coupled to the third conductive region and extending between the fifth and sixth memory cells; and
a fourth polysilicon material coupled to the fourth conductive region and extending between the seventh and eighth memory cells.