IP Library Granted Patent US 8,426,976
Granted Patent B2
US 8,426,976 · App. 12/392,636 · Granted Apr 23, 2013

Non-volatile semiconductor storage device and method of manufacturing the same

Inventors: Megumi Ishiduki (Yokohama, JP); Hideaki Aochi (Kawasaki, JP); Ryota Katsumata (Yokohama, JP); Hiroyasu Tanaka (Tokyo, JP); Masaru Kidoh (Komae, JP); Masaru Kito (Yokohama, JP); Yoshiaki Fukuzumi (Yokohama, JP); Yosuke Komori (Yokohama, JP); Yasuyuki Matsuoka (Yokohama, JP)
Assignee: Kabushiki Kaisha Toshiba
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,426,976
App. No.
12/392,636
Granted
Apr 23, 2013
Kind
B2
Abstract

A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.

Claims (58)

1. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series,

each of the memory strings comprising:

a columnar semiconductor layer extending in a direction perpendicular to a substrate;

a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and

interlayer insulation layers formed above or below the conductive layers,

a sidewall of each of the conductive layers facing the columnar semiconductor layer being formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof, and

a sidewall of each of the interlayer insulation layers facing the columnar semiconductor layer being formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.

2. The non-volatile semiconductor storage device according to claim 1 , wherein

a sidewall of the conductive layers facing the columnar semiconductor layer is formed at positions farther away from the columnar semiconductor layer than a sidewall of the interlayer insulation layers facing the columnar semiconductor layer.

3. The non-volatile semiconductor storage device according to claim 2 , wherein

the memory layers are charge accumulation layers that are configured to be able to accumulate charges.

4. The non-volatile semiconductor storage device according to claim 3 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein voids are formed between the charge accumulation layers and the columnar semiconductor layer.

5. The non-volatile semiconductor storage device according to claim 3 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein the second insulation layer is formed integrally and continuously with the entire side surface of the columnar semiconductor layer.

6. The non-volatile semiconductor storage device according to claim 2 , wherein

the memory layers have resistance-varying devices.

7. The non-volatile semiconductor storage device according to claim 6 , wherein

respective ends of the conductive layers in contact with the memory layers configure diodes.

8. The non-volatile semiconductor storage device according to claim 1 , wherein

the memory layers are charge accumulation layers that are configured to be able to accumulate charges.

9. The non-volatile semiconductor storage device according to claim 8 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein voids are formed between the charge accumulation layers and the columnar semiconductor layer.

10. The non-volatile semiconductor storage device according to claim 8 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein the second insulation layer is formed integrally and continuously with the entire side surface of the columnar semiconductor layer.

11. The non-volatile semiconductor storage device according to claim 1 , wherein

the memory layers have resistance-varying devices.

12. The non-volatile semiconductor storage device according to claim 11 , wherein

respective ends of the conductive layers in contact with the memory layers configure diodes.

13. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series,

each of the memory strings comprising:

a columnar semiconductor layer extending in a direction perpendicular to a substrate;

a plurality of conductive layers formed at the side of the sidewall of the columnar semiconductor layer via memory layers; and

interlayer insulation layers formed one above the other with the conductive layers,

a sidewall of the conductive layers facing the columnar semiconductor layer being formed at positions farther away from the columnar semiconductor layer than a sidewall of the interlayer insulation layers facing the columnar semiconductor layer; and

the sidewall of each of the conductive layers having a first incline and the sidewall of each of the interlayer insulation layers having a second incline different from the first incline.

14. The non-volatile semiconductor storage device according to claim 13 , wherein

the memory layers are charge accumulation layers that are configured to be able to accumulate charges.

15. The non-volatile semiconductor storage device according to claim 13 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein voids are formed between the charge accumulation layers and the columnar semiconductor layer.

16. The non-volatile semiconductor storage device according to claim 13 , comprising:

a first insulation layer formed between the charge accumulation layers and the conductive layers; and

a second insulation layer formed between the charge accumulation layers and the columnar semiconductor layer,

wherein the first insulation layer is formed integrally and continuously with the entire side surface of the columnar semiconductor layer.

17. The non-volatile semiconductor storage device according to claim 13 , wherein

the memory layers have resistance-varying devices.

18. The non-volatile semiconductor storage device according to claim 17 , wherein

respective ends of the conductive layers in contact with the memory layers configure diodes.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2009
From: ISHIDUKI, MEGUMI; AOCHI, HIDEAKI; KATSUMATA, RYOTA; TANAKA, HIROYASU; KIDOH, MASARU; KITO, MASARU; FUKUZUMI, YOSHIAKI; KOMORI, YOSUKE; MATSUOKA, YASUYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022632/0294 →
Priority Claims (1)
JP 2008-65886 · Mar 14, 2008 · national
Continuity (1)
Related Publication 20090230458A1 · Sep 17, 2009