Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
1. An apparatus comprising:
a silicon film for providing a channel to a plurality of charge storage transistors in a NAND string;
a first charge storage structure surrounding the silicon film at a first location;
a second charge storage structure surrounding the silicon film at a second location, the second location vertically offset from the first location;
a first dielectric structure provided between the first charge storage structure and the silicon film, and between the second charge storage structure and the silicon film, wherein the first dielectric structure has a first surface in contact with the silicon film and an opposing surface in contact with the first charge storage structure, the second charge storage structure, and the second dielectric structure;
first and second word lines respectively provided opposite to the first and second charge storage structures, the first and second word lines each having a respective planar vertical surface adjacent the respective first and second charge storage structures;
a second dielectric structure extending horizontally between the first and second word lines;
a third dielectric structure extending between the first word line and the first charge storage structure, the third dielectric structure including at least first and second dielectric materials, wherein a vertical dimension of the first dielectric material is greater than a vertical dimension of the first charge storage structure, and wherein a vertical dimension of the second dielectric material is greater than the vertical dimensions of the planar vertical surface of the first word line and of the first charge storage structure; and
a fourth dielectric structure extending between the second word line and the second charge storage structure, the fourth dielectric structure including at least third and fourth dielectric materials, wherein a vertical dimension of the third dielectric material is greater than a vertical dimension of the second charge storage structure, and wherein a vertical dimension of the fourth dielectric material is greater than the vertical dimensions of the planar vertical surface of the second word line and of the second charge storage structure.
2. The apparatus of claim 1 , wherein:
the first dielectric material and the third material each comprise a silicon dioxide layer; and
wherein the second dielectric material and the fourth material structure each comprise at least a silicon nitride layer.
3. The apparatus of claim 1 , wherein a cross-section of the silicon film is U-shaped.
4. The apparatus of claim 1 , wherein the first charge storage structure comprises a ring of doped polysilicon around the silicon film at the first location, and the second charge storage structure comprises a ring of doped polysilicon around the silicon film at the second location.
5. The apparatus of claim 4 , wherein:
the first word line and the second word line each comprise a metal; and
wherein each of the first and second word lines surrounds the respective ring of doped polysilicon.
6. The apparatus of claim 1 , wherein the first and second charge storage structures each comprise polysilicon.
7. A method comprising:
forming a silicon film in a vertical opening for providing a channel to a plurality of charge storage transistors in a NAND string;
forming a first charge storage structure surrounding the silicon film at a first vertical location;
forming a second charge storage structure surrounding the silicon film at a second vertical location, the second vertical location being vertically offset from the first vertical location;
forming a first dielectric structure between the first charge storage structure and the silicon film, and between the second charge storage structure and the silicon film;
forming first and second word lines respectively provided laterally opposite to the first and second charge storage structures, the first and second word lines each having a respective planar vertical surface adjacent the respective first and second charge storage structures;
forming a second dielectric structure extending horizontally between the first and second word lines;
forming a third dielectric structure extending between the first word line and the first charge storage structure, the third dielectric structure including at least first and second dielectric materials, wherein a vertical dimension of the first dielectric material is greater than a vertical dimension of the first charge storage structure, and wherein a vertical dimension of the second dielectric material is greater than the vertical dimensions of the planar vertical surface of the first word line and of the first charge storage structure; and
forming a fourth dielectric structure extending between the second word line and the second charge storage structure, the fourth dielectric structure including at least third and fourth dielectric materials, wherein a vertical dimension of the third dielectric material is greater than a vertical dimension of the second charge storage structure, and wherein a vertical dimension of the fourth dielectric material is greater than the vertical dimensions of the planar vertical surface of the second word line and of the second charge storage structure.
8. The method of claim 7 , wherein the planar vertical surfaces of the first and second word lines have a vertical height that is less than a vertical height of the respective first and second charge storage structures.
9. The method of claim 7 , wherein forming the first dielectric structure and the second dielectric structure comprises forming a silicon dioxide layer.
10. The method of claim 7 , wherein forming the first charge storage structure comprises forming a ring of doped polysilicon around the silicon film at the first vertical location, and wherein forming the second charge storage structure comprises forming a ring of doped polysilicon around the silicon film at the second vertical location.
11. The method of claim 7 , wherein forming the first and second word lines comprises forming the first and second word lines comprising a metallic material.