Charge storage apparatus and methods
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.
1. A memory structure, comprising:
a vertical string of charge storage devices, each charge storage device including a respective charge storage structure surrounding a vertical film comprising polysilicon and forming a vertical film channel structure, and wherein each charge storage structure in the string is spaced from at least one vertically adjacent charge storage structure by a respective dielectric tier, and wherein each charge storage structure extends between and contacts vertically adjacent dielectric tiers;
a first dielectric structure between a first side of each of the charge storage devices of the vertical string and the vertical film channel structure; and
a second dielectric structure on a second side of the respective charge storage structures of the vertical string, the second dielectric structure extending between the charge storage structures and a respective gate surrounding the charge storage structure, the respective gates having a planar vertical surface extending adjacent the charge storage structure, the second dielectric structure having multiple dielectric materials, including a first dielectric material extending concentric to a respective charge storage structure and having a vertical dimension greater than the vertical dimension of the respective charge storage structure and a second dielectric material having a vertical dimension greater than the vertical dimensions of the adjacent charge storage structure and greater than the vertical dimension of the planar vertical surface of the adjacent gate.
2. The memory structure of claim 1 , wherein each charge storage structure includes a floating gate comprising polysilicon.
3. The memory structure of claim 1 , wherein the respective gates comprise metal.
4. The memory structure of claim 1 , wherein:
the first dielectric structure comprises silicon dioxide or silicon nitride; and
the second dielectric structure comprises one or more of silicon dioxide and silicon nitride.
5. The memory structure of claim 4 , wherein the first dielectric material of the second dielectric structure comprises an oxide, and wherein the second dielectric material of the second dielectric structure comprises a nitride, and wherein the second dielectric structure further comprises a third dielectric material comprising oxide on the opposite side of the nitride from the first dielectric material.
6. The memory structure of claim 1 , wherein the vertical pillar comprises a portion of a U-shaped pipe.
7. The memory structure of claim 1 , wherein the first dielectric structure forms a tunneling dielectric.
8. The memory structure of claim 1 , wherein the respective gates are each part of metal word lines extending between the respective dielectric tiers.