Computing reduction and prefix sum operations in memory
View Patent ↗The present disclosure includes apparatuses and methods for computing reduction and prefix sum operations in memory. A number of embodiments include processing circuitry configured to compute a reduction operation on data stored in a group of memory cells by splitting the data into a plurality of elements, copying each of the plurality of elements into elements that are wider than before being copied, and performing a logical operation associated with the reduction operation on each of the copied elements.
1. An apparatus, comprising:
processing circuitry configured to compute at least one of a reduction operation and a prefix sum operation on data stored in a group of memory cells;
wherein the processing circuitry is on layout pitch with sense lines of the group of memory cells.
2. The apparatus of claim 1 , wherein the reduction operation includes:
splitting the data into a plurality of elements;
copying each of the plurality of elements into elements that are wider than before being copied; and
performing a logical operation on each of the copied elements.
3. The apparatus of claim 2 , wherein each of the copied elements are twice as wide as before being copied.
4. The apparatus of claim 2 , wherein each of the copied elements are half as tall as before being copied.
5. The apparatus of claim 2 , wherein the logical operation is an addition operation.
6. The apparatus of claim 2 , wherein the logical operation is a multiplication operation.
7. A method of operating processing circuitry, comprising:
computing at least one of a reduction operation and a prefix sum operation on data stored in a group of memory cells;
wherein the at least one of the reduction operation and the prefix sum operation is computed without transferring the data via an input/output (I/O) line external to the group of memory cells.
8. The method of claim 7 , wherein:
the group of memory cells are included in an array of memory cells; and
the I/O line is external to the array of memory cells.
9. The method of claim 7 , wherein the prefix sum operation includes:
splitting the data into a plurality of elements;
copying each of the plurality of elements into elements that are wider than before being copied; and
performing a logical operation on each of the copied elements.
10. The method of claim 9 , wherein splitting the data into a plurality of elements includes splitting the data into even and odd indexed elements.
11. The method of claim 10 , wherein the logical operation combines the even and odd indexed elements.
12. The method of claim 9 , wherein the prefix sum operation includes:
shifting an output of the logical operation;
performing an additional logical operation on the shifted output and one of the copied elements; and
packing an output of the additional logical operation into elements that are less wide than before the additional logical operation.
13. The method of claim 7 , wherein the method includes storing a result of the at least one of the reduction operation and the prefix sum operation in the group of memory cells without transferring the data via the I/O line.
14. The method of claim 7 , wherein the method includes outputting a result of the at least one of the reduction operation and the prefix sum operation to external hardware or an external register via the I/O line.
15. The method of claim 7 , wherein the method includes computing the at least one of the reduction operation and the prefix sum operation using a sense amplifier and a compute component of the processing circuitry.
16. An apparatus, comprising:
processing circuitry configured to compute at least one of a reduction operation and a prefix sum operation on data stored in a group of memory cells;
wherein the processing circuitry is configured to compute the at least one of the reduction operation and the prefix sum operation without transferring the data via a bus external to the group of memory cells.
17. The apparatus of claim 16 , wherein:
the apparatus includes an array of memory cells that includes the group of memory cells; and
the bus is external to the array of memory cells.
18. The apparatus of claim 16 , wherein the processing circuitry comprises sensing circuitry.
19. The apparatus of claim 16 , wherein the processing circuitry is configured to store a result of the at least one of the reduction operation and the prefix sum operation in the group of memory cells without transferring the data via the bus.
20. The apparatus of claim 16 , wherein the prefix sum operation is a forward prefix sum operation or a backward prefix sum operation.