IP Library Granted Patent US 10,269,626
Granted Patent B2
US 10,269,626 · App. 15/867,017 · Granted Apr 23, 2019

Stair step formation using at least two masks

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Quick Facts
Patent No.
US 10,269,626
App. No.
15/867,017
Granted
Apr 23, 2019
Kind
B2
Abstract

Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.

Claims (10)

1. A method, comprising:

forming a first mask over a conductive material to define a first exposed area;

forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area smaller than the first exposed area;

forming a plurality of conductive lines comprising a stack of alternating conductive materials and insulating materials; and

forming a plurality of strings of memory cells coupled to respective conductive lines of the plurality of conductive lines, wherein the stack of alternating conductive materials and insulating materials have a stair step structure formed at an edge of the stack.

2. The method of claim 1 , wherein forming the plurality of strings of memory cells comprises forming a plurality of non-linear strings of memory cells.

3. The method of claim 2 , wherein forming the plurality of non-linear strings of memory cells comprises forming a plurality of U-shaped strings of memory cells.

4. The method of claim 1 , wherein forming the plurality of strings of memory cells comprises forming a plurality of linear strings of memory cells.

5. The method of claim 4 , wherein forming the plurality of linear strings of memory cells comprises forming the plurality of linear memory cells such that they are arranged substantially orthogonal to the plurality of conductive lines.

6. The method of claim 1 , wherein the second mask is formed of a material that has an etching rate greater than that of the first mask.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2018
From: HA, CHANG WAN; WOLSTENHOLME, GRAHAM R.; THIMMEGOWDA, DEEPAK
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044586/0242 →