Compensating for memory input capacitance
Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).
1. An apparatus, comprising:
a memory die coupled with an inductive region;
an access line coupled with the inductive region; and
a memory controller coupled with the access line, the memory controller operable to transmit a signal modulated with a modulation scheme having at least three levels through the access line to the memory die, wherein the inductive region is configured to alter a capacitance of the access line based at least in part on the transmission of the signal.
2. The apparatus of claim 1 , further comprising:
a bond pad coupled with the access line and a substrate; and
a die pad coupled with the memory die, wherein the inductive region of the access line is coupled with the bond pad and the die pad of the memory die.
3. The apparatus of claim 1 , wherein the inductive region and is configured in a shape of a coil.
4. The apparatus of claim 1 , wherein the access line comprises a redistribution layer (RDL) coupled with a die pad of the memory die, and wherein the inductive region is embedded within a substrate.
5. The apparatus of claim 1 , wherein the access line comprises a redistribution layer (RDL), and wherein the inductive region is positioned above a substrate and is coupled with a die pad of the memory die.
6. The apparatus of claim 1 , wherein the access line, or the inductive region, or both are embedded within a substrate.
7. The apparatus of claim 1 , wherein the inductive region is positioned above a die pad coupled with the memory die.
8. The apparatus of claim 1 , further comprising:
a second memory die in a second layer coupled with a substrate, the second memory die configured to receive a second signal; and
a second access line coupled with a second inductive region coupled with the second memory die, wherein the second inductive region is configured to compensate for capacitance of the second access line based at least in part on the transmission of the signal to the memory die.
9. The apparatus of claim 1 , further comprising:
a ball grid array (BGA) pad coupled with a substrate, wherein the memory die is embedded in an epoxy mold compound (EMC), wherein the access line comprises a redistribution layer (RDL), and wherein the access line is coupled with the BGA pad.
10. An apparatus, comprising:
an access line coupled with an inductive region;
the inductive region coupled with a memory die;
the memory die coupled with a substrate; and
a memory controller coupled with the access line, the memory controller operable to transmit a signal modulated with a modulation scheme having multiple levels to the memory die, wherein the inductive region is configured to alter a capacitance of the access line in response to the transmission of the signal.
11. The apparatus of claim 10 , further comprising:
a second access line coupled with a second inductive region coupled with a second memory die, wherein the second inductive region is configured to alter the capacitance of the second access line based at least in part on a reflection of at least a part of the signal.
12. The apparatus of claim 11 , wherein the access line comprises the inductive region and the second access line comprises the second inductive region.
13. The apparatus of claim 11 , wherein the memory die and the second memory die are different memory dies in a same package.
14. The apparatus of claim 11 , wherein each of the access line and the second access line comprise a redistribution layer (RDL).
15. The apparatus of claim 10 , wherein the inductive region comprises a first inductive segment extending in a first direction, and a second inductive segment extending in a second direction different from the first direction.
16. The apparatus of claim 10 , wherein the inductive region is positioned above the substrate coupled with the memory die and is coupled with a die pad of the memory die.
17. The apparatus of claim 10 , wherein the access line is coupled with a pad of the memory die, and wherein the inductive region is embedded within the substrate coupled with the memory die.
18. The apparatus of claim 10 , wherein the access line is coupled with a pad of the memory die, and wherein the inductive region is in contact with the substrate coupled with the memory die.
19. A method, comprising:
transmitting a signal through an access line to a memory die that is coupled with a substrate, the access line coupled with an inductive region coupled with the memory die, wherein the signal is modulated with a modulation scheme having at least three levels; and
receiving the signal at the memory die, wherein the inductive region is configured to alter a capacitance of the access line based at least in part on receiving the signal.
20. The method of claim 19 , wherein the inductive region is configured to alter the capacitance of the access line based at least in part on receiving a reflection of at least part of the signal from a second memory die coupled with the substrate.