IP Library Granted Patent US 10,535,415
Granted Patent B2
US 10,535,415 · App. 15/802,597 · Granted Jan 14, 2020

Trim setting determination for a memory device

Inventors: Aswin Thiruvengadam (Folsom, CA); Daniel L. Lowrance (El Dorado Hills, CA); Peter Feeley (Boise, ID)
Assignee: Micron Technology, Inc.
G11C29/028G06F12/0246G06F12/0292G11C16/10G06F2212/7207G11C2029/4402
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Quick Facts
Patent No.
US 10,535,415
App. No.
15/802,597
Granted
Jan 14, 2020
Kind
B2
Abstract

Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

Claims (19)

1. An apparatus, comprising a controller with control circuitry configured to:

receive operational characteristics of an array of memory cells based on prior operations performed by the array of the memory cells, wherein the controller is in a different geographic location than the array of memory cells;

determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells; and

send the set of trim settings to the array of memory cells.

2. The apparatus of claim 1 , wherein the trim settings are configured for static data.

3. The apparatus of claim 1 , wherein the trim settings are configured for dynamic data.

4. The apparatus of claim 1 , wherein the operational characteristics include programming operation speed for the array of memory cells.

5. The apparatus of claim 4 , wherein the trim settings are configured for the programming operation speed for the array of memory cells.

6. The apparatus of claim 1 , wherein the operational characteristics include life span for the array of memory cells.

7. The apparatus of claim 6 , wherein the trim settings are configured for the life span of the array of memory cells.

8. A method, comprising:

receiving operational characteristics at a controller from an array of memory cells based on prior operations performed by the array of memory cells; and

determining, by the controller, a set of trim settings for the first array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells; and

sending the set of trim settings from the controller to the array of memory cells, wherein the array of memory cells is in a different geographic location than the controller.

9. The method of claim 8 , further including requesting operational characteristics of the array of memory cells before receiving operational characteristics of the array of memory cells.

10. The method of claim 8 , wherein sending the set of trim settings to the array of memory cells includes sending trim settings configured for static data.

11. The method of claim 8 , wherein sending the set of trim settings to the array of memory cells includes sending trim settings configured for dynamic data.

12. The method of claim 8 , wherein receiving operational characteristics from the array of memory cells includes receiving programming operational speed for the array of memory cells.

13. The method of claim 8 , wherein receiving operational characteristics from the array of memory cells includes receiving life span for the array of memory cells.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2017
From: THIRUVENGADAM, ASWIN; LOWRANCE, DANIEL L.; FEELEY, PETER
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044026/0323 →
Continuity (1)
Related Publication 20190139619A1 · May 9, 2019