Resistive memory cell structures and methods

1. A method of forming an array of resistive memory cells, the method comprising:

forming a first number of resistive memory cells in a first region of the array, the first number of cells comprising a first resistance variable material;

forming a second number of resistive memory cells in a second region of the array, the second number of cells comprising a second resistance variable material that is different than the first resistance variable material;

forming a first via in a dielectric formed on the first region and the second region of the array;

forming a first resistance variable material on the first and the second region of the array, the first resistance variable material filling the first via;

forming a first cap material on the first resistance variable material;

removing a portion of the first resistance variable material and a portion of the first cap material from the second region of the array;

forming a second via in the dielectric formed on the second region of the array;

forming a second resistance variable material on the first and second region of the array, the second resistance variable material filling the second via;

forming a second cap material on the second resistance variable material;

removing the second resistance variable material and the second cap material from the first region of the array; and

performing an etch process such that the first resistance variable material is confined to the first via and the second resistance variable material is confined to the second via.

2. The method of claim 1 , wherein the first and second resistance variable materials include different chalcogenide alloys.