Method for 3D ink jet TCB interconnect control
View Patent ↗A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions.
1. A semiconductor device assembly comprising:
a first substrate, wherein the first substrate comprises a first semiconductor device;
a second substrate disposed over the first substrate, wherein the second substrate comprises a second semiconductor device;
at least one pillar that extends from the second substrate towards the first substrate, the at least one pillar comprising a copper portion positioned adjacent to the second substrate, a solder portion, and a nickel portion between the copper portion and the solder portion;
and
a barrier positioned on at least a portion of an exterior of the at least one pillar, the barrier having a first end and a second end, the second end being castellated and wherein the barrier prevents electromigration of solder from the solder portion into the copper portion of the at least one pillar.
2. The semiconductor device assembly of claim 1 , wherein the at least one pillar extends towards a pad positioned over a trace on the first substrate.
3. The semiconductor device assembly of claim 1 , wherein the first end of the barrier is positioned adjacent to the second substrate and the second end of the barrier is located a first distance from the second substrate and wherein a plurality of slots of the castellated second end of the barrier are located a second distance from the second substrate, the second distance being less than the first distance.
4. The semiconductor device assembly of claim 3 , wherein the plurality of slots are configured to permit expansion of solder in a first plurality of directions.
5. The semiconductor device assembly of claim 4 , wherein the barrier is configured to prevent expansion of solder in a second plurality of directions.
6. The semiconductor device assembly of claim 3 , wherein the first distance extends from the second substrate, past the copper portion and nickel portion of the at least one pillar, and is adjacent to a portion of the solder portion of the at least one pillar, and wherein the second distance extends from the second substrate to the nickel portion of the at least one pillar.
7. The semiconductor device assembly of claim 1 , wherein at least a portion of the barrier extends from a second surface of the second substrate to a first surface of the first substrate.
8. The semiconductor device assembly of claim 7 , further comprising a pad on the first surface of the first substrate positioned within the portion of the barrier that extends to the first surface of the first substrate.
9. The semiconductor device assembly of claim 8 , wherein the portion of the barrier that extends to the first surface of the first substrate is configured to retain the pad in alignment with the at least one pillar.
10. The semiconductor device assembly of claim 7 , wherein the portion of the barrier that extends to the first surface of the first substrate supports the second substrate on the first surface of the first substrate.
11. The semiconductor device assembly of claim 1 , comprising underfill material positioned between the first substrate and the second substrate, the barrier positioned between the at least one pillar and the underfill material.
12. A semiconductor device comprising:
a substrate;
a plurality of pillars extending from a surface of the substrate, each pillar having a first portion comprised of copper adjacent to the surface, a second portion comprised of nickel adjacent to the first portion, and a third portion comprised of solder adjacent to the second portion, the second portion separating the third portion from the first portion; and
a barrier on a portion of an exterior of each pillar, a first end of the barrier being adjacent to the surface of the substrate and a second end of the barrier positioned a first distance away from the surface of the substrate, the barrier prevents electromigration of solder from the third portion into the first portion of the pillar and wherein the second end of each barrier is castellated with a plurality of windows through the second end of each barrier.
13. The semiconductor device of claim 12 , wherein each portion of the barrier adjacent to the windows is a second distance away from the surface, the second distance being less than the first distance.
14. The semiconductor device of claim 13 , wherein the second distance extends to at least the second portion of each pillar comprised of nickel.
15. The semiconductor device of claim 14 , wherein the first distance extends to at least the third portion of each pillar comprised of solder.
16. The semiconductor device of claim 13 , wherein the plurality of windows for each barrier are located at horizontal directions with respect to horizontal and vertical directions, the horizontal directions located in a horizontal plane.
17. The semiconductor device of claim 13 , wherein the first distance extends from the surface of the substrate to the third portion of the pillar, and wherein the second distance extends from the surface of the substrate to the second portion of the pillar.
18. The semiconductor device of claim 12 , wherein the barriers are comprised of one of polyimides, polyimide-like materials, polymers, epoxies, epoxy-acrylates, and solder mask materials.