IP Library Granted Patent US 10,236,037
Granted Patent B2
US 10,236,037 · App. 15/874,117 · Granted Mar 19, 2019

Data transfer in sensing components

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Quick Facts
Patent No.
US 10,236,037
App. No.
15/874,117
Granted
Mar 19, 2019
Kind
B2
Abstract

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might include an array of memory cells. An example apparatus might also include a plurality of sensing components coupled to the array and comprising a first group of sensing components coupled to a controller via a first number of control lines and a second group of sensing components coupled to the controller via a second number of control lines wherein the controller is configured to activate at least one of the first number of control lines and the second number of control lines.

Claims (46)

1. An apparatus, comprising:

an array of memory cells;

a controller coupled to the array;

a first group of first sensing components coupled to the controller by a first number of control lines;

a second group of second sensing components coupled to the controller by a second number of control lines;

wherein the controller is configured to selectively equilibrate first sense amplifiers of the first sensing components while the first sense amplifiers are not activated, while second sense amplifiers of the second sensing components are not equilibrated, and while the second sense amplifiers are activated;

wherein the first sensing components are configured to transfer data from first compute components of the first sensing components to the first sense amplifiers while the first sense amplifiers are equilibrated and not activated; and

wherein the second sensing components are configured to transfer data from the second sense amplifiers to second compute components of the second sensing components while the second sense amplifiers are activated and not equilibrated.

2. The apparatus of claim 1 , wherein:

the first sensing components are configured to transfer the data from the first compute components to the first sense amplifiers in response to the controller activating first logical operation selection logic components of the first sensing components; and

the second sensing components are configured to transfer the data from the second sense amplifiers to the second compute components in response to the controller activating second logical operation selection logic components of the second sensing components while the first logical operation selection logic components are activated.

3. The apparatus of claim 1 , wherein the first sensing components are configured to transfer the data from the first compute components to the first sense amplifiers without data stored in the second compute components being updated.

4. The apparatus of claim 1 , wherein the data transferred from the second sense amplifiers to the second compute components is first data, wherein the controller is configured to, before the first data is transferred the second compute components, activate the second sense amplifiers to transfer the first data from memory cells of the array to the second sense amplifiers.

5. The apparatus of claim 1 , wherein the selective equilibration of the respective first sense amplifiers by the controller removes data from the first sense amplifiers.

6. The apparatus of claim 1 , wherein the controller being configured to selectively equilibrate the first sense amplifiers comprises the controller being configured to selectively short pairs of data lines coupled to the first sense amplifiers.

7. The apparatus of claim 1 , wherein controller is configured to charge pairs of data lines coupled to the first sense amplifiers and pairs of data lines coupled to the second sense amplifiers while the first sense amplifiers and the second sense amplifiers are equilibrated.

8. The apparatus of claim 1 , wherein the first sensing components are configured to transfer the data from the first compute components to the first sense amplifiers without modifying data stored in the first compute components.

9. The apparatus of claim 1 , wherein the controller is configured to:

select an access line coupled to a first group of memory cells of the array coupled to the first group of first sensing components and a second group of memory cells of the array coupled to the second group of first sensing components; and

to activate the first sense amplifiers and the second sense amplifiers concurrently while the access line is selected and while the first sense amplifiers and the second sense amplifier are not equilibrated to move data from the first group of memory cells to the first sense amplifiers and to move data from the second group of memory cells to the second sense amplifiers concurrently.

10. The apparatus of claim 9 , wherein:

the controller being configured to selectively equilibrate the first sense amplifiers comprises the controller being configured to selectively remove the data from the first sense amplifiers by selectively equilibrating first sense amplifiers,

the controller is configured to retain the data moved to the second sense amplifiers by not equilibrating the sense amplifiers; and

the retained data is the data that is transferred from the second sense amplifiers to second compute components.

11. A method, comprising:

moving first data from first memory cells to first sense amplifiers of first sensing components of a group of the first sensing components and moving second data from second memory cells to second sense amplifiers of second sensing components of a group of the second sensing components concurrently, wherein the group of the first sensing components and group second of the second sensing components are coupled to different control lines;

removing the first data from the first sense amplifiers by equilibrating the first sense amplifiers;

transferring third data in first compute components of the first sensing components to the first sense amplifiers while the first sense amplifiers are equilibrated; and

transferring the second data from the second sense amplifiers to second compute components of the second sensing components while the second sense amplifiers are not equilibrated and while transferring the third data in the first compute components to the first sense amplifiers.

12. The method of claim 11 , wherein transferring the third data in the first compute components to the first sense amplifiers occurs without modifying the third data in the first compute components.

13. The method of claim 11 , wherein transferring the second data from the second sense amplifiers to the second compute components occurs without updating the third data in the first compute components.

14. The method of claim 11 , wherein:

transferring the third data to the first sense amplifiers occurs while the first sense amplifiers are deactivated and while logical operation selection logic components of the first sensing components are activated; and

transferring the second data from the second sense amplifiers to the second compute components occurs while the second sense amplifiers are activated and while logical operation selection logic components of the second sensing components are activated.

15. The method of claim 11 , wherein moving the first data from first memory cells to the first sense amplifiers and moving second data from second memory cells to the second sense amplifiers occurs while an access line coupled to the first memory cells and the second memory cells is activated and while the first sense amplifiers and the second sense amplifiers are activated.

16. The method of claim 15 , wherein moving the first data from first memory cells to the first sense amplifiers and moving second data from second memory cells to the second sense amplifiers occurs while the first sense amplifiers and the second sense amplifiers are not equilibrated.

17. An apparatus, comprising:

an array of memory cells comprising first and second groups of memory cells coupled to an access line;

a controller coupled to the array;

a group of first sensing components coupled to the first group of memory cells and coupled to the controller by a first number of control lines; and

a group of second sensing components coupled to the second group of memory cells and coupled to the controller by a second number of control lines;

wherein the controller is configured to select the access line and activate first sense amplifiers of the group of first sensing components to transfer first data from the first group of memory cells to the activated first sense amplifiers while the first sense amplifiers are not equilibrated, and while second sense amplifiers of the group of second sensing components are equilibrated and not activated; and

wherein the controller is configured to activate second sense amplifiers of the group of second sensing components to move second data from the second sense amplifiers to compute components of the group of second sensing components and from the second sense amplifiers to second group of memory cells concurrently while the second sense amplifiers are not equilibrated, while the first sense amplifiers not are equilibrated and activated, and while the access line is selected.

18. The apparatus of claim 17 , wherein the second sensing components are configured to transfer the second data from the second compute components to the second sense amplifiers while the second sense amplifiers are equilibrated and not activated.

19. The apparatus of claim 18 , wherein the second data is transferred from the second compute components to the second sense amplifiers in response to the controller activating logical operation selection logic components of the group of second sensing components.

20. The apparatus of claim 17 , wherein the first data is transferred from the first group of memory cells to the activated first sense amplifiers while logical operation selection logic components of the group of first sensing components is not activated, and wherein the first sensing components are configured to transfer the first data from the activated first sense amplifiers to compute components of the group of first sensing components in response to the controller activating the logical operation selection logic components while the first sense amplifiers are not equilibrated.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 18, 2018
From: WILLCOCK, JEREMIAH J.; HUSH, GLEN E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044653/0731 →