Input buffer circuit

1. An apparatus comprising:

first and second voltage terminals;

first, second, and third circuit nodes, a potential of the first circuit node being changed based on an input signal;

a flip-flop circuit comprising first and second inverters cross-coupled to each other, the first inverter being coupled between the first voltage terminal and the second circuit node;

a first transistor coupled between the second and third circuit nodes, the first transistor having a control electrode coupled to the first circuit node; and

a first current control circuit coupled between the third circuit node and the second voltage terminal, an amount of current flowing through the first current control circuit being controlled based on a first code signal.

2. The apparatus of claim 1 , further comprising:

a fourth circuit node; and

a second transistor coupled between the fourth circuit node and the first circuit node,

wherein the second transistor having a control electrode supplied with the input signal.

3. The apparatus of claim 2 , further comprising a third transistor coupled between the first voltage terminal and the fourth circuit node,

wherein the third transistor is brought into an ON state when a timing signal is in an active state.

4. The apparatus of claim 3 , wherein the first circuit node is connected to the second voltage terminal when the timing signal is in an inactive state.

5. The apparatus of claim 3 , further comprising:

fifth, sixth, seventh circuit nodes;

a fourth transistor coupled between the sixth and seventh circuit nodes, the fourth transistor having a control electrode coupled to the fifth circuit node; and

a second current control circuit coupled between the seventh circuit node and the second voltage terminal, an amount of current flowing through the second current control circuit being controlled based on a second code signal,

wherein the second inverter being coupled between the first voltage terminal and the sixth circuit node.

6. The apparatus of claim 5 , further comprising a fifth transistor coupled between the fourth circuit node and the fifth circuit node.

7. The apparatus of claim 6 , wherein the fifth transistor having a control electrode supplied with a reference voltage.

8. The apparatus of claim 6 , wherein the fifth circuit node is connected to the second voltage terminal when the timing signal is in an inactive state.

9. The apparatus of claim 5 , wherein the amount of current flowing through the first current control circuit is different from the amount of current flowing through the second current control circuit.

10. The apparatus of claim 5 , further comprising a fuse circuit storing the first and second code signals.

11. The apparatus of claim 5 ,

wherein the first current control circuit comprises a plurality of sixth transistors coupled in parallel, and

wherein the second current control circuit comprises a plurality of seventh transistors coupled in parallel.

12. The apparatus of claim 11 ,

wherein at least two of the sixth transistors have different size from each other, and

wherein at least two of the seventh transistors have different size from each other.

13. The apparatus of claim 11 ,

wherein at least one of the sixth transistors is fixed to an ON state regardless of the first code signal, and

wherein at least one of the seventh transistors is fixed to an ON state regardless of the second code signal.

14. The apparatus of claim 11 , wherein all the sixth transistors or all the seventh transistors are in an ON state.

15. An apparatus comprising:

first and second voltage terminals;

first, second, third, and fourth circuit nodes;

a flip-flop circuit comprising first and second inverters cross-coupled to each other, the first inverter being coupled between the first voltage terminal and the first circuit node, the second inverter being coupled between the first voltage terminal and the third circuit node;

a first transistor coupled between the first and second circuit nodes;

a second transistor coupled between the third and fourth circuit nodes;

a plurality of third transistors coupled in parallel between the second circuit node and the second voltage terminal; and

a plurality of fourth transistors coupled in parallel between the fourth circuit node and the second voltage terminal.

16. The apparatus of claim 15 , wherein the plurality of third transistors are supplied with a first logic level in common to control electrodes thereof.

17. The apparatus of claim 16 ,

wherein one or more of the plurality of fourth transistors are supplied with the first logic level in common to control electrodes thereof, and

wherein remaining one or more of the plurality of fourth transistors are supplied with a second logic level in common to control electrodes thereof.

18. An apparatus comprising:

a first amplifier configured to generate first and second voltages by amplifying an input signal;

a third transistor configured to generate a third voltage by amplifying the first voltage;

a fourth transistor configured to generate a fourth voltage by amplifying the second voltage;

a latch circuit configured to latch a data indicated by a difference between the third and fourth voltages;

a first current control circuit configured to adjust a source current flowing through the third transistor; and

a second current control circuit configured to adjust a source current flowing through the fourth transistor.

19. The apparatus of claim 18 ,

wherein the first amplifier comprises a first transistor configured to receive the input signal to a control electrode thereof and a second transistor configured to receive a reference voltage,

wherein the first voltage is generated by the first transistor, and

wherein the second voltage is generated by the second transistor.

20. The apparatus of claim 19 ,

wherein the third transistor is coupled between the latch circuit and the first current control circuit, the third transistor being configured to receive the first voltage to a control electrode thereof, and

wherein the fourth transistor is coupled between the latch circuit and the second current control circuit, the fourth transistor being configured to receive the second voltage to a control electrode thereof.

21. An apparatus comprising:

first and second voltage terminals;

a first transistor coupled between the first voltage terminal and a first circuit node, the first transistor comprising a control gate configured to receive an input signal;

a second transistor coupled between the first voltage terminal and a second circuit node, the second transistor comprising a control gate coupled to the first circuit node;

a third transistor coupled between the second circuit node and the second voltage terminal, the third transistor comprising a control gate configured to receive a code signal;

a fourth transistor coupled between the first voltage terminal and a third circuit node, the fourth transistor comprising a control gate configured to receive a second input signal;

a fifth transistor coupled between the first voltage terminal and a fourth circuit node, the fifth transistor comprising a control gate configured to be coupled to the third circuit node: and

a sixth transistor coupled between the fourth circuit node and the second voltage terminal, the sixth transistor comprising a control gate configured to receive a second code signal.

22. The apparatus of claim 21 , further comprising:

a flip-flop circuit coupled among the first voltage terminal, the second transistor and the fifth transistor.