IP Library Granted Patent US 10,409,726
Granted Patent B2
US 10,409,726 · App. 15/797,812 · Granted Sep 10, 2019

Dynamic L2P cache

Inventor: Sebastien Andre Jean (Meridian, ID)
Assignee: Micron Technology, Inc.
G06F12/0871G06F9/5016G06F9/544G06F12/0246
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Quick Facts
Patent No.
US 10,409,726
App. No.
15/797,812
Granted
Sep 10, 2019
Kind
B2
Abstract

Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

Claims (52)

1. A method performed by a controller of a NAND memory device, the controller in communication with a volatile memory, the method comprising:

determining a command queue depth of the NAND memory device;

determining that a command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of read commands to write commands exceeds the determined threshold ratio, reallocating an amount of volatile memory allocated to a donor memory location to a Logical to Physical (L2P) cache; and

storing additional L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

2. A NAND memory device comprising:

a volatile memory;

a controller, the controller executing instructions performing operations of:

determining a command queue depth of the NAND memory device;

determining that a command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of read commands to write commands exceeds the determined threshold ratio, reallocating an amount of volatile memory allocated to a donor memory location to a Logical to Physical (L2P) cache; and

storing additional L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

3. The NAND memory device of claim 2 , wherein the donor memory location is a read buffer.

4. The NAND memory device of claim 2 , wherein the donor memory location is a write buffer.

5. The NAND memory device of claim 2 , wherein the donor memory location is a portion of both a read buffer and a write buffer.

6. A non-transitory machine-readable medium, storing instructions, which when executed by a machine, causes the machine to perform operations comprising:

determining a command queue depth of a NAND memory device;

determining that a command queue depth exceeds a determined threshold number of commands and a ratio of read commands to write commands exceeds a determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of read commands to write commands exceeds the determined threshold ratio, reallocating an amount of volatile memory allocated to a donor memory location to a Logical to Physical (L2P) cache; and

storing additional L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the donor memory location and now allocated to the L2P cache as a result of increasing the L2P cache.

7. The non-transitory machine-readable medium of claim 6 , wherein the donor memory location is a read buffer.

8. The non-transitory machine-readable medium of claim 6 , wherein the donor memory location is a write buffer.

9. The non-transitory machine-readable medium of claim 6 , wherein the donor memory location is a portion of both a read buffer and a write buffer.

10. The method of claim 1 , wherein the donor memory location is a portion of a write buffer.

11. The method of claim 10 , further comprising:

subsequent to the storing additional L2P table entries, determining that the command queue depth no longer exceeds the determined threshold number of commands; and

responsive to determining that the command queue depth no longer exceeds the determined threshold number of commands, decreasing a size of the L2P cache by reallocating at least a portion of the amount of volatile memory back to the donor memory location.

12. The method of claim 1 , wherein the method further comprises, subsequent to the storing additional L2P table entries in the L2P cache:

determining the command queue depth of the NAND memory device;

determining that the command queue depth exceeds the determined threshold number of commands and a ratio of write commands to read commands exceeds a second determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of write commands to write commands exceeds the second determined threshold ratio, reallocating a second amount of volatile memory allocated to a read buffer to the Logical to Physical (L2P) cache; and

storing further L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the read buffer and now allocated to the L2P cache as a result of increasing the L2P cache.

13. The NAND memory device of claim 2 , wherein the donor memory location is a portion of a write buffer.

14. The NAND memory device of claim 2 , wherein the operations performed by the controller further comprise:

subsequent to the storing additional L2P table entries, determining that the command queue depth no longer exceeds the determined threshold number of commands; and

responsive to determining that the command queue depth no longer exceeds the determined threshold number of commands, decreasing a size of the L2P cache by reallocating at least a portion of the amount of volatile memory back to the donor memory location.

15. The NAND memory device of claim 14 , wherein the operations performed by the controller further comprise:

subsequent to the storing additional L2P table entries in the L2P cache:

determining the command queue depth of the NAND memory device;

determining that the command queue depth exceeds the determined threshold number of commands and a ratio of write commands to read commands exceeds a second determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of write commands to write commands exceeds the second determined threshold ratio, reallocating a second amount of volatile memory allocated to a read buffer to the Logical to Physical (L2P) cache; and

storing further L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the read buffer and now allocated to the L2P cache as a result of increasing the L2P cache.

16. The non-transitory machine-readable medium of claim 6 , wherein the donor memory location is a portion of a write buffer.

17. The non-transitory machine-readable medium of claim 16 , wherein the operations further comprise:

subsequent to the storing additional L2P table entries, determining that the command queue depth no longer exceeds the determined threshold number of commands; and

responsive to determining that the command queue depth no longer exceeds the determined threshold number of commands, decreasing a size of the L2P cache by reallocating at least a portion of the amount of volatile memory back to the donor memory location.

18. The non-transitory machine-readable medium of claim 17 , wherein the operations further comprise:

subsequent to the storing additional L2P table entries in the L2P cache:

determining the command queue depth of the NAND memory device;

determining that the command queue depth exceeds the determined threshold number of commands and a ratio of write commands to read commands exceeds a second determined threshold ratio;

responsive to determining that the command queue depth exceeds the determined threshold number of commands and the ratio of write commands to write commands exceeds the second determined threshold ratio, reallocating a second amount of volatile memory allocated to a read buffer to the Logical to Physical (L2P) cache; and

storing further L2P table entries in the L2P cache in a region of the volatile memory previously allocated to the read buffer and now allocated to the L2P cache as a result of increasing the L2P cache.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2018
From: JEAN, SEBASTIEN ANDRE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045161/0890 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
Continuity (1)
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