Systems and methods for temperature sensor access in die stacks
A memory device may include a memory array including a plurality of memory cells and a die stack including at least a portion of the plurality of memory cells. The memory device may also include multiple temperature sensors each designed to output a temperature code corresponding to the temperature of a respective die of the die stack. One die of the die stack is then designed to output the temperature code corresponding to the hottest die of the die stack.
1. A memory device comprising:
a memory array comprising a plurality of memory cells, wherein the memory device comprises a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM);
a die stack comprising at least a portion of the plurality of memory cells; and
a plurality of temperature sensors each configured to output a temperature code corresponding to the temperature of a respective die of the die stack, wherein a first die of the die stack comprises compare logic configured to compare the temperature code of the first die of the die stack to the temperature code of a second die of the die stack and to output the temperature code corresponding to the hottest die between the first die and the second die based on the comparison, and wherein one die of the die stack is configured to output the temperature code corresponding to the hottest die of the die stack.
2. The memory device of claim 1 , wherein the plurality of temperature sensors are on-die temperature sensors.
3. The memory device of claim 1 , wherein each die of the die stack has a separate temperature sensor.
4. The memory device of claim 1 , wherein the temperature code of the first die of the die stack is communicated to the second die by a through silicon via (TSV).
5. The memory device of claim 1 , wherein the temperature code corresponding to the hottest die between the first die and the second die is communicated to the compare logic of a third die of the die stack for comparison to the temperature code of the third die.
6. The memory device of claim 1 , wherein the temperature code corresponding to the hottest die of the die stack is output to a mode register of a master die of the die stack.
7. The memory device of claim 6 , wherein the mode register is configured to be read and output the temperature code of the hottest die of the die stack for use in designating a refresh rate of the memory device.
8. The memory device of claim 7 , wherein the refresh rate of the memory device is increased in response to the temperature code of the hottest die of the die stack increasing beyond a threshold temperature.
9. The memory device of claim 1 , wherein the temperature code is representative of a temperature range.
10. The memory device of claim 1 , wherein the die stack comprises 4 die.
11. The memory device of claim 1 , comprising a plurality of die stacks.