Reprogrammable non-volatile ferroelectric latch for use with a memory controller

1. An electronic memory apparatus, comprising;

an array of memory cells;

a controller in electronic communication with the array of memory cells; and

a latch in electronic communication with the controller and exclusive of the array of memory cells, the latch including:

a first ferroelectric cell in electronic communication with a sense component via a first conductive line;

a second ferroelectric cell in electronic communication with the sense component via a second conductive line;

a switching component configured to selectively couple the first conductive line with a voltage source;

a second switching component configured to selectively couple the first conductive line with a ground node; and

a first isolation component positioned between the switching component and the sense component and positioned between the second switching component and the sense component.

2. The electronic memory apparatus of claim 1 , wherein the switching component is configured to selectively couple the first conductive line with the voltage source.

3. The electronic memory apparatus of claim 2 ,

wherein the second switching component is configured to selectively couple the first conductive line with the ground node.

4. The electronic memory apparatus of claim 1 ,

wherein the first isolation component is positioned between the first ferroelectric cell and the sense component, the first isolation component configured to isolate the sense component from the first ferroelectric cell.

5. The apparatus of claim 1 , wherein the controller is configured to access the latch faster than the controller is configured to access the array of memory cells.

6. The electronic memory apparatus of claim 1 , wherein the latch further comprises:

a first ferroelectric capacitor coupled between the voltage source and the first conductive line; and

a second ferroelectric capacitor coupled between the voltage source and the second conductive line, wherein the first ferroelectric capacitor and the second ferroelectric capacitor each comprise the same ferroelectric material as the first ferroelectric cell and the second ferroelectric cell.

7. The electronic memory apparatus of claim 1 , wherein:

a plate of the first ferroelectric cell is coupled with the voltage source via a first switching component and with the ground node via the second switching component; and

a plate of the second ferroelectric cell is coupled with the voltage source via a third switching component and with the ground node via a fourth switching component.

8. The electronic memory apparatus of claim 1 , wherein at least one of the first conductive line or the second conductive line is configured as an input or an output of the latch.

9. The electronic memory apparatus of claim 1 , wherein the array of memory cells includes a plurality of ferroelectric memory cells.

10. A method, comprising:

receiving a first value from an array of ferroelectric memory cells;

receiving a second value from the array of ferroelectric memory cells;

activating a first switching component to couple a conductive line with a voltage source;

writing the first value to a first ferroelectric cell in electronic communication with a first node of a sense component, wherein writing the first value further comprises coupling an access line of the first ferroelectric cell to a ground node via a second switching component;

isolating the first ferroelectric cell from the sense component via a first isolation component while writing the first value, wherein the first isolation component is positioned between the first switching component and the sense component and positioned between the second switching component and the sense component;

writing the second value to a second ferroelectric cell in electronic communication with a second node of the sense component, wherein a latch exclusive of the array of ferroelectric memory cells comprises the first ferroelectric cell and the second ferroelectric cell; and

coupling the conductive line that connects the first ferroelectric cell with the first node of the sense component to the voltage source or the ground node based at least in part on a logic state of the first value being written to the first ferroelectric cell.

11. The method of claim 10 , further comprising:

sensing the first value from the first ferroelectric cell;

sensing the second value from the second ferroelectric cell; and

outputting a stored value determined by the sense component to the array of ferroelectric memory cells, wherein the stored value is based at least in part on the first value and the second value.

12. The method of claim 11 , wherein sensing the first value further comprises:

applying a first voltage to a plate of the first ferroelectric cell; and

coupling, using the first isolation component, the first ferroelectric cell with the sense component.

13. The method of claim 11 , wherein sensing the second value further comprises:

applying a second voltage to a plate of the second ferroelectric cell; and

coupling, using a second isolation component, the second ferroelectric cell with the sense component.

14. The method of claim 10 , wherein writing the first value further comprises:

coupling a plate of the first ferroelectric cell to the voltage source via the first switching component.

15. The method of claim 10 , further comprising:

isolating the second ferroelectric cell from the sense component via a second isolation component while writing the second value.

16. The method of claim 10 , further comprising:

precharging the first ferroelectric cell and the second ferroelectric cell before performing an access operation using the first ferroelectric cell and the second ferroelectric cell.

17. The method of claim 16 , wherein precharging the first ferroelectric cell and the second ferroelectric cell further comprises:

coupling a plate of the first ferroelectric cell and the access line of the first ferroelectric cell to the ground node; and

coupling a plate of the second ferroelectric cell and an access line of the second ferroelectric cell to the ground node.

18. An electronic memory apparatus, comprising:

an array of ferroelectric memory cells;

a latch exclusive of the array of ferroelectric memory cells and comprising a first ferroelectric cell and a second ferroelectric cell;

a switching component configured to selectively couple a conductive line with a voltage source;

a second switching component configured to selectively couple the conductive line with a ground node; and

a sense component in electronic communication with the first ferroelectric cell and the second ferroelectric cell;

a first isolation component positioned between the switching component and the sense component and positioned between the second switching component and the sense component; and

a controller in electronic communication with a plurality of transistors, wherein the controller is operable to:

sense a first value from the first ferroelectric cell;

sense a second value from the second ferroelectric cell;

output a stored value determined by the sense component to the array of ferroelectric memory cells; and

couple the conductive line that connects the first ferroelectric cell with a first node of the sense component to the voltage source or the ground node based at least in part on a logic state of the first value being written to the first ferroelectric cell.

19. The electronic memory apparatus of claim 18 , wherein the controller is further operable to:

isolate the first ferroelectric cell from the sense component via the first isolation component while writing the first value; and

isolate the second ferroelectric cell from the sense component via a second isolation component while writing the second value.