Memory cells and memory arrays

1. A memory cell, comprising:

a conductive gate;

a charge-blocking region adjacent the conductive gate; the charge-blocking region comprising silicon oxynitride and silicon dioxide and having an upper surface and a lower surface, each of the upper and lower surfaces contacting an insulative material;

a charge-storage region adjacent the charge-blocking region;

a tunneling region adjacent the charge-storage region, the tunneling region comprising a first tunneling material and a second tunneling material, the first tunneling material being directly against the charge-storage region and extending elevationally from the upper surface to the lower surface, the second tunneling material being against the first tunneling material and having first regions extending to an elevation above the upper surface and second regions extending elevationally below the lower surface, the first and second regions being in physical contact with vertical surfaces of the insulative material; and

a channel material adjacent the tunneling material, the tunneling material being between the channel material and the charge-storage region, the conductive gate, the charge-blocking region, the charge-storage region and the tunneling material having concave vertical faces.

2. The memory cell of claim 1 wherein the charge-blocking region comprises the silicon oxynitride proximate the conductive gate, and comprises the silicon dioxide spaced from the conductive gate by the silicon oxynitride.

3. The memory cell of claim 2 wherein the silicon oxynitride of the charge-blocking region is directly against a dielectric barrier region, and wherein the dielectric barrier region is directly against conductive material of the conductive gate.

4. The memory cell of claim 1 wherein the silicon dioxide of the charge-blocking region is directly against the charge-storage region.

5. The memory cell of claim 1 wherein the charge-storage region comprises silicon nitride, and wherein the silicon nitride is directly against the silicon dioxide of the charge-blocking region.

6. The memory cell of claim 1 wherein the charge-blocking region has a thickness between the conductive gate and the charge-storage region which is within a range of from about 50 Å to about 150 Å, and wherein the silicon dioxide of the charge-blocking region has a thickness between the conductive gate and the charge-storage region which is within a range of from about 10 Å to about 30 Å.

7. A memory array, comprising:

a vertical stack of alternating insulative levels and wordline levels;

a channel material extending vertically along the stack;

the wordline levels comprising conductive regions; the conductive regions being spaced from the channel material by gaps;

the insulative levels comprising ledges above and below at least portions of the gaps;

charge-storage regions within the gaps; the charge-storage regions being vertically spaced from one another by intervening regions of the ledges, the charge-storage regions having upper surfaces and lower surfaces, each of the upper and lower surfaces contacting an insulative material of the insulative levels;

charge-blocking regions within the gaps and between the charge-storage regions and the conductive regions; the charge-blocking regions comprising silicon dioxide extending vertically along silicon oxynitride; the silicon dioxide being between the silicon oxynitride and the charge-storage regions, the charge-storage regions and the charge-blocking regions having curved vertical faces; and

charge tunneling regions adjacent the charge-storage regions, the tunneling region comprising a first tunneling material that extends only along the wordline levels and a second tunneling material that extends along the wordline levels and extends along and directly against the insulative levels.

8. The memory array of claim 7 wherein the channel material serpentines along the vertical direction, with segments of the channel material along the insulative levels projecting inwardly, and with segments of the channel material along the conductive levels projecting outwardly.

9. The memory array of claim 8 wherein the conductive regions have concave vertical faces.

10. The memory array of claim 7 wherein the charge-storage regions comprise silicon nitride.

11. The memory array of claim 7 wherein the silicon oxynitride of the charge-blocking regions has a first horizontal thickness and the silicon dioxide of the charge-blocking regions has a second horizontal thickness; and wherein the first horizontal thickness as at least about double the first horizontal thickness.

12. The memory array of claim 7 wherein the second tunneling material extends along the channel material, and wherein the insulative ledges are directly against the second tunneling material.

13. The memory array of claim 7 wherein the first tunneling material is adjacent the charge-storage material and directly against top and bottom surfaces of the ledges.

14. The memory array of claim 7 further comprising a third tunneling material between the second tunneling material and the channel material.