IP Library Granted Patent US 10,282,093
Granted Patent B2
US 10,282,093 · App. 15/722,054 · Granted May 7, 2019

Sequential memory access operations

Inventor: Toru Tanzawa (Tokyo, JP)
Assignee: Micron Technology, Inc.
G06F3/0604G06F3/0611G06F3/0625G06F3/0659G06F3/0679G06F12/06G06F12/0623G06F12/14G06F13/1657G06F13/1694G06F2212/1024G06F2212/1028G06F2212/1052G06F2212/214G06F2212/2532Y02D10/14
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Quick Facts
Patent No.
US 10,282,093
App. No.
15/722,054
Granted
May 7, 2019
Kind
B2
Abstract

Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Claims (17)

1. A method of operating a memory, comprising:

obtaining an address corresponding to a memory access operation;

storing the address corresponding to the memory access operation to a first storage of the memory;

performing the memory access operation;

obtaining an address corresponding to a subsequent memory access operation;

storing the address corresponding to the subsequent memory access operation to a second storage of the memory;

suspending the memory access operation and storing the address corresponding to the memory access operation to a third storage of the memory;

sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation;

transferring the address corresponding to the subsequent memory access operation to the first storage of the memory;

performing the subsequent memory access operation;

stopping the subsequent memory access operation;

sharing charge between access lines used for the subsequent memory access operation and access lines to be used for resuming the memory access operation;

transferring the address corresponding to the memory access operation to the first storage of the memory; and

resuming the memory access operation.

2. The method of claim 1 , wherein obtaining the address corresponding to the memory access operation comprises determining that address by an internal controller of the memory from an address corresponding to a prior memory access operation.

3. The method of claim 1 , wherein storing the address corresponding to the memory access operation to the first storage of the memory comprises storing the address corresponding to the memory access operation to a primary register of an address register of the memory, wherein storing the address corresponding to the subsequent memory access operation to the second storage of the memory comprises storing the address corresponding to the subsequent memory access operation to a secondary register of the address register, and wherein storing the address corresponding to the memory access operation to the third storage of the memory comprises storing the address corresponding to the memory access operation to an additional register of the address register.

4. The method of claim 1 , wherein sharing charge between the access lines used for the subsequent memory access operation and the access lines to be used for resuming the memory access operation comprises sharing that charge without discharging the access lines used for the memory access operation after sharing charge between the access lines used for the memory access operation and the access lines to be used for the subsequent memory access operation.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
Continuity (3)
Continuation 15244163 · Aug 23, 2016
Continuation 14479703 · Sep 8, 2014
Related Publication 20180046375A1 · Feb 15, 2018