Semiconductor package with embedded MIM capacitor, and method of fabricating thereof

1. An interposer, comprising:

a first redistribution layer comprising an interconnect structure;

a single layer of organic material directly on the first redistribution layer;

a capacitor embedded in the single layer of organic material, the capacitor extending between two opposing surfaces of the single layer of organic material and comprising a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, the first electrode directly electrically connecting with a surface of the interconnect structure of the first redistribution layer at one of the two opposing surfaces of the single layer of organic material;

a single hard mask having a surface directly on another of the two opposing surfaces of the single layer of organic material;

a first continuous conductive pillar embedded in and extending through the single layer of organic material and the single hard mask, the first continuous conductive pillar directly electrically connecting with the interconnect structure of the first redistribution layer at the one of the two opposing surfaces of the single layer of organic material; and

a second redistribution layer comprising an interconnect structure having a surface directly on a surface of the single hard mask opposite the surface of the single hard mask on the another of the two opposing surfaces of the single layer of organic material, the interconnect structure of the second redistribution layer directly electrically connecting with the second electrode at the surface of the single hard mask opposite the surface thereof on the another of the two opposing surfaces of the single layer of organic material through a second continuous conductive pillar extending from the second electrode through the single hard mask between the surface thereof directly on the another of the two opposing surfaces of the single layer of organic material and the surface thereof opposite the surface thereof on the another of the two opposing surfaces of the single layer of organic material, and the interconnect structure of the second redistribution layer directly electrically connecting with the first continuous conductive pillar at the surface of the single hard mask on the another of the two opposing surfaces of the single layer of organic material.

2. The interposer of claim 1 , wherein the first electrode surrounds the second electrode and is coaxial with the second electrode.

3. The interposer of claim 1 , wherein the first electrode has a surface in contact with the surface of the interconnect structure of the first redistribution layer, the surface of the first electrode and the surface of the interconnect structure of the first redistribution layer meeting along a common plane.

4. The interposer of claim 1 , wherein the second electrode has a surface in contact with the surface of the single hard mask, the surface of the second electrode and the surface of the single hard mask meeting along a common plane.

5. The interposer of claim 1 , wherein the first continuous conductive pillar has a surface in contact with the surface of the interconnect structure of the second redistribution layer, the surface of the first continuous conductive pillar and the surface of the interconnect structure of the second redistribution layer meeting along a common plane.

6. The interposer of claim 1 , further comprising a microbump extending through a passivation material on a surface of the first redistribution layer opposite the single layer of organic material and electrically connecting with the interconnect structure of the first redistribution layer.

7. A semiconductor package, comprising:

the interposer of claim 1 ;

a microbump electrically connecting with the interconnect structure of the first redistribution layer through a passivation material on a surface of the first redistribution layer opposite the single layer of organic material; and

a chip connecting with the microbump.

8. The semiconductor package of claim 7 , wherein the first electrode surrounds the second electrode and is coaxial with the second electrode.

9. The semiconductor package of claim 7 , wherein the second electrode has a surface meeting the surface of the single hard mask along a common plane.

10. A method of fabricating a semiconductor package, comprising:

forming a single layer of organic material on a first redistribution layer comprising an interconnect structure;

embedding a capacitor in the single layer of organic material, the capacitor extending between two opposing surfaces of the single layer of organic material and comprising a first electrode, a second electrode, and a capacitor dielectric between the first electrode and the second electrode, the first electrode directly electrically connecting with a surface of the interconnect structure of the first redistribution layer at one of the two opposing surfaces of the single layer of organic material;

forming a single hard mask having a surface directly on another of the two opposing surfaces of the single layer of organic material;

embedding a first continuous conductive pillar in and extending through the single layer of organic material and the single hard mask to directly electrically connect the first continuous conductive pillar with the interconnect structure of the first redistribution layer at the one of the two opposing surfaces of the single layer of organic material;

forming a second redistribution layer comprising an interconnect structure having a surface directly on a surface of the single hard mask opposite the surface of the single hard mask on the another of the two opposing surfaces of the single layer of organic material to electrically connect with the second electrode at the surface of the single hard mask opposite the surface thereof on the another of the two opposing surfaces of the single layer of organic material through a second continuous conductive pillar extending from the second electrode through the single hard mask between the surface thereof directly on the another of the two opposing surfaces of the single layer of organic material, and the interconnect structure of the second redistribution layer directly electrically connecting with the first continuous conductive pillar at the surface of the single hard mask on the another of the two opposing surfaces of the single layer of organic material;

forming a microbump through a passivation layer on a surface of the first redistribution layer opposite the single layer of organic material to electrically connect with the interconnect structure of the first redistribution layer; and

connecting a chip with the microbump.

11. The method of claim 10 , wherein embedding the capacitor in the single layer of organic material comprises:

forming a trench in the single layer of organic material to expose the first redistribution layer;

forming the first electrode in the trench;

forming the capacitor dielectric on the first electrode; and

forming the second electrode on the capacitor dielectric.

12. The method of claim 10 , wherein embedding the first continuous conductive pillar in the single hard mask and the single layer of organic material comprises:

etching the single layer of organic material through a hole in the single hard mask to form a trench to expose the first redistribution layer; and

forming the first continuous conductive pillar in the trench.

13. The method of claim 10 , further comprising embedding the second continuous conductive pillar in the single hard mask between the second electrode and the interconnect structure of the second redistribution layer.

14. The method of claim 10 , before forming the single layer of organic material on the first redistribution layer, further comprising forming the first redistribution layer on passivation material, and embedding the microbump in the passivation material in contact with the interconnect structure of the first redistribution layer.