Memory device write circuitry
View Patent ↗Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.
1. A memory device comprising:
a main input-output line;
driving circuitry configured to generate a main input-output signal on the main input-output line; and
a plurality of sensing amplifier coupled to the main input-output line and each configured to be written to or transmit data over the main input-output line, wherein each sensing amplifier comprises:
a local data line;
local data line generation circuitry configured to generate a local data signal on the local data line, wherein the local data line generation circuitry comprises a gate transistor in series with a pull-down transistor, wherein the gate transistor is configured to receive a write enable signal to control whether the pull-down transistor coupling to the low voltage is completed, and wherein the local data line generation circuitry is configured to block connection of a local false line to the low voltage via a complementary pull-down transistor when the pull-down transistor couples the local data line to the low voltage; and
a plurality of local sensing amplifiers coupled to the local data line generation circuitry via the local data line.
2. The memory device of claim 1 comprising a main input-output false line that is complementary to the main input-output line, wherein the main input-output false line is generated by the driving circuitry.
3. The memory device of claim 2 , wherein the local data line generation circuitry generates the local false line using the main input-output false line, wherein the local false line is complementary to the local data line.
4. The memory device of claim 1 , wherein the local data line generation circuitry comprises a pull-down transistor that is configured to receive the main input-output line at a gate of the pull-down transistor and selectively couple the local data line to a low voltage.
5. The memory device of claim 1 , wherein the local data line comprises a pair of cross-p-channel transistors that are configured to respond to a connection of the local data line to the low voltage by connecting the local false line to a high voltage and to respond to a connection of the local false line to the low voltage through the complementary pull-down transistor by connecting the local data line to a high voltage.
6. The memory device of claim 1 , wherein the driving circuitry is configured to set the main input-output signal based at least in part on a write enable signal.
7. The memory device of claim 6 , wherein the driving circuitry is configured to set the main input-output signal based on a data signal.