IP Library Granted Patent US 10,348,270
Granted Patent B2
US 10,348,270 · App. 15/834,892 · Granted Jul 9, 2019

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device

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Quick Facts
Patent No.
US 10,348,270
App. No.
15/834,892
Granted
Jul 9, 2019
Kind
B2
Abstract

Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Claims (49)

1. An apparatus, comprising:

a register configured to store impedance calibration information;

programmable termination resistances having a programmable impedance;

an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances, the impedance calibration circuit further configured to program the impedance calibration information in the register related to the calibration operation; and

an arbitration engine configured activate the impedance calibration engine to perform the calibration operation responsive to obtaining control over an external resistance.

2. The apparatus of claim 1 wherein the impedance calibration information related to the calibration operation comprises an indication that the calibration operation has completed.

3. The apparatus of claim 1 wherein the impedance calibration information related to the calibration operation comprises an indication that the calibration parameters have been updated following the calibration operation.

4. The apparatus of claim 1 wherein the impedance calibration circuit comprises:

an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters; and

an impedance calibration controller configured to initiate the calibration operation and further configured to program the register with impedance calibration information.

5. The apparatus of claim 1 wherein the impedance calibration circuit comprises:

an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters; and

an impedance calibration controller configured to initiate the calibration operation, the impedance calibration controller comprising:

an impedance calibration flag circuit configured to program impedance calibration information in the register; and

impedance calibration control logic configured to cause the impedance calibration flag circuit to program the impedance calibration information.

6. The apparatus of claim 1 wherein the impedance calibration circuit comprises:

an impedance calibration controller configured to initiate the calibration operation; and

an impedance calibration engine configured to perform the calibration operation responsive to being activated and determine the calibration parameters, the impedance calibration engine comprising:

calibration engine control logic configured to receive a calibration start signal to activate the calibration engine to initiate calibration operations; and

a calibration parameter storage circuit to store calibration parameters for a plurality of frequency set points.

7. A method, comprising:

arbitrating for control over an external resistance;

initiating a background impedance calibration operation, wherein the impedance calibration operation is initiated responsive to obtaining control over the external resistance;

performing the impedance calibration operation to determine calibration parameters for setting impedance of programmable termination resistances included in the semiconductor device; and

programming impedance calibration information in a mode register of the semiconductor responsive to the calibration operation.

8. The method of claim 7 , further comprising:

applying the calibration parameters to set the impedance of the programmable termination resistances.

9. The method of claim 8 wherein applying the calibration parameters to set the impedance of the programmable termination resistances is responsive to a calibration latch command.

10. The method of claim 7 , further comprising:

latching the calibration parameters responsive to a calibration latch command.

11. The method of claim 7 wherein the background impedance calibration operation is initiated responsive to power up of a semiconductor device.

12. The method of claim 7 wherein the calibration operation comprises:

determining calibration parameters to set impedance of adjustable pull-down termination components of the programmable termination resistances; and

determining calibration parameters to set impedance of adjustable pull-up termination components of the programmable termination resistances.

13. The method of claim 12 wherein determining calibration parameters to set impedance of the adjustable pull-up termination components of the programmable termination resistances comprises determining the calibration parameters for the adjustable pull-down termination components based on the impedance of the adjustable pull-down termination components.

14. The method of claim 7 wherein performing the impedance calibration operation to determine calibration parameters comprises:

determining calibration parameters to set impedance of adjustable pull-down termination components of the programmable termination resistances based on an external ZQ resistor.

15. The method of claim 7 , further comprising:

receiving an adjustable pull-up termination components calibration command; and

determining calibration parameters to set impedance of adjustable pull-up termination components of the programmable termination resistances responsive to the adjustable pull-up termination components calibration command.

16. The method of claim 15 wherein the adjustable pull-up termination components calibration command is received when a power supply voltage is at a second voltage that is greater than a first voltage.

17. The method of claim 15 , further comprising:

applying the calibration parameters to set the impedance of the adjustable pull-up termination components responsive to a change in frequency set point.

18. The method of claim 7 , further comprising:

receiving an adjustable pull-down termination components calibration command; and

determining calibration parameters to set impedance of adjustable pull-down termination components of the programmable termination resistances responsive to the adjustable pull-down termination components calibration command.

19. The method of claim 18 wherein the adjustable pull-down termination components calibration command is received when a power supply voltage is at a second voltage that is greater than a first voltage.

20. The method of claim 18 , further comprising:

applying the calibration parameters to set the impedance of the adjustable pull-down termination components responsive to a change in frequency set point.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065012/0688 →
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050716/0678 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 7 TO PATENT SECURITY AGREEMENT Recorded Feb 6, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 045267/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2017
From: GANS, DEAN
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044508/0820 →