Charge separation for memory sensing

1. A method of operating memory, comprising:

applying a sensing voltage to a memory cell;

determining a data state of the memory cell based, at least in part, on a comparison of:

an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time; and

an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time;

coupling a first capacitor to the memory cell using a first transistor upon a first signal being applied to the first transistor, wherein the first signal is applied to the first transistor before the particular reference time such that the first capacitor is coupled to the memory cell before the particular reference time and;

coupling a second capacitor to the memory cell using a second transistor upon a second signal being applied to the second transistor, wherein the second signal is applied to the second transistor after the particular reference time such that the second capacitor is coupled to the memory cell after the particular reference time.

2. The method of claim 1 , wherein the method includes:

determining the amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before the particular reference time using the first capacitor; and

determining the amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time using the second capacitor.

3. The method of claim 1 , wherein the particular reference time corresponds to a time at which a change of a polarization state of a ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the memory cell is in a particular data state.

4. The method of claim 1 , wherein the method includes:

determining the data state of the memory cell is a first data state upon the comparison indicating the amount of charge discharged by the memory cell before the particular reference time is greater than the amount of charge discharged by the memory cell after the particular reference time; and

determining the data state of the memory cell is a second data state upon the comparison indicating the amount of charge discharged by the memory cell before the particular reference time is less than the amount of charge discharged by the memory cell after the particular reference time.

5. The method of claim 1 , wherein the comparison of the amount of charge discharged by the memory cell before the particular reference time and the amount of charge discharged by the memory cell after the particular reference time includes a comparison of a signal associated with the amount of charge discharged by the memory cell before the particular reference time and a signal associated with the amount of charge discharged by the memory cell after the particular reference time.

6. The method of claim 1 , wherein the sensing voltage applied to the memory cell is applied as a single pulse.

7. An apparatus, comprising:

a memory cell;

a first capacitor configured to store charge discharged by the memory cell while a sensing voltage is being applied to the memory cell before a particular reference time;

a first transistor configured to couple the first capacitor to the memory cell upon a first signal being applied to the first transistor, wherein the first signal is applied to the first transistor before the particular reference time such that the first capacitor is coupled to the memory cell before the particular reference time;

a second capacitor configured to store charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time;

a second transistor configured to couple the second capacitor to the memory cell upon a second signal being applied to the second transistor, wherein the second signal is applied to the second transistor after the particular reference time such that the second capacitor is coupled to the memory cell after the particular reference time; and

circuitry configured to determine a data state of the memory cell based, at least in part, on a comparison of the charge stored by the first capacitor and the charge stored by the second capacitor.

8. The apparatus of claim 7 , wherein:

the particular reference time is a time that occurs after a first reference time while the sensing voltage is being applied to the memory cell and before a second reference time that is subsequent to the first reference time while the sensing voltage is being applied to the memory cell, wherein:

the first reference time corresponds to a time at which the memory cell will have discharged half of its charge when the memory cell is in a first data state; and

the second reference time corresponds to a time at which the memory cell will have discharged half of its charge when the memory cell is in a second data state.

9. The apparatus of claim 7 , wherein:

the data state of the memory cell is a first data state when the comparison indicates the charge stored by the first capacitor is greater than the charge stored by the second capacitor; and

the data state of the memory cell is a second data state when the comparison indicates the charge stored by the first capacitor is less than the charge stored by the second capacitor.

10. A method of operating memory, comprising:

applying a sensing voltage to a memory cell;

determining a data state of the memory cell based, at least in part, on a comparison of:

an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a first reference time; and

an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after a second reference time that is subsequent to the first reference time;

coupling a first capacitor to the memory cell using a first transistor upon a first signal being applied to the first transistor, wherein the first signal is applied to the first transistor before the particular reference time such that the first capacitor is coupled to the memory cell before the particular reference time and;

coupling a second capacitor to the memory cell using a second transistor upon a second signal being applied to the second transistor, wherein the second signal is applied to the second transistor after the particular reference time such that the second capacitor is coupled to the memory cell after the particular reference time.

11. The method of claim 10 , wherein:

the first reference time is before a time at which a change of a polarization state of a ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the memory cell is in a particular data state; and

the second reference time is after the time at which the change of the polarization state of the ferroelectric material of the memory cell will occur while the sensing voltage is being applied to the memory cell if the memory cell is in the particular data state.

12. The method of claim 10 , wherein the method includes:

determining the data state of the memory cell is a first data state upon the comparison indicating the amount of charge discharged by the memory cell before the first reference time is greater than the amount of charge discharged by the memory cell after the second reference time; and

determining the data state of the memory cell is a second data state upon the comparison indicating the amount of charge discharged by the memory cell before the first reference time is less than the amount of charge discharged by the memory cell after the second reference time.

13. The method of claim 10 , wherein the method includes pre-charging a data line to which the memory cell is coupled before applying the sensing voltage to the memory cell.

14. The method of claim 13 , wherein the method includes varying an amount by which the data line to which the memory cell is coupled is pre-charged.

15. An apparatus, comprising:

a memory cell;

a first capacitor configured to store charge discharged by the memory cell while a sensing voltage is being applied to the memory cell before a first reference time;

a first transistor configured to couple the first capacitor to the memory cell upon a first signal being applied to the first transistor, wherein the first signal is applied to the first transistor before a particular reference time such that the first capacitor is coupled to the memory cell before the particular reference time;

a second capacitor configured to store charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after a second reference time that is subsequent to the first reference time;

a second transistor configured to couple the second capacitor to the memory cell upon a second signal being applied to the second transistor, wherein the second signal is applied to the second transistor after the particular reference time such that the second capacitor is coupled to the memory cell after the particular reference time; and

circuitry configured to determine a data state of the memory cell based, at least in part, on a comparison of the charge stored by the first capacitor and the charge stored by the second capacitor.

16. The apparatus of claim 15 , wherein:

the first reference time corresponds to a time at which the memory cell will have discharged half of its charge if the memory cell is in a first data state; and

the second reference time corresponds to a time at which the memory cell will have discharged half of its charge if the memory cell is in a second data state.

17. The apparatus of claim 15 , wherein the circuitry includes a latch configured to perform the comparison of the charge stored by the first capacitor and the charge stored by the second capacitor.

18. The apparatus of claim 15 , wherein the circuitry is configured to determine the data state of the memory cell without using a reference voltage.

19. The apparatus of claim 15 , wherein an amount of time between the first reference time and the second reference time is 5-10 nanoseconds.

20. A method of operating memory, comprising:

applying a first sensing voltage that is less than a particular voltage to a memory cell,

applying a second sensing voltage that is greater than the particular voltage to the memory cell after applying the first sensing voltage to the memory cell; and

determining a data state of the memory cell based, at least in part, on a comparison of:

an amount of charge discharged by the memory cell while the first sensing voltage is being applied to the memory cell, wherein the memory cell is determined to be in the first data state when the amount of charge discharged by the memory cell while the first sensing voltage being applied to a memory cell is greater than the amount of charge discharged by the memory cell while the second sensing voltage is being applied to the memory cell; and

an amount of charge discharged by the memory cell while the second sensing voltage is being applied to the memory cell, wherein the memory cell is determined to be in the second data state when the amount of charged discharged by the memory cell while the first sensing voltage being applied to a memory cell is less than the amount of charge discharged by the memory cell while the second sensing voltage is being applied to the memory cell.

21. The method of claim 20 , wherein the particular voltage corresponds to a voltage that will cause a polarization state of a ferroelectric material of the memory cell to change while that voltage is being applied to the memory cell if the memory cell is in a particular polarization state.

22. The method of claim 20 , wherein the method includes applying the first sensing voltage to the memory cell and applying the second sensing voltage to the memory cell during a same sense operation being performed on the memory cell.

23. An apparatus, comprising:

a memory cell;

a first capacitor configured to store charge discharged by the memory cell while a first sensing voltage that is less than a particular voltage is being applied to the memory cell;

a second capacitor configured to store charge discharged by the memory cell while a second sensing voltage that is greater than the particular voltage is being applied to the memory cell, wherein the second sensing voltage is applied to the memory cell after the first sensing voltage;

a cascode coupled to the memory cell;

a first transistor coupled to the cascode and configured to couple the first capacitor to the memory cell through the cascode upon a first signal being applied to the first transistor; and

a second transistor coupled to the cascode and configured to couple the second capacitor to the memory cell through the cascode upon a second signal being applied to the second transistor; and

circuitry configured to determine a data state of the memory cell based, at least in part on a comparison of the charge stored by the first capacitor and the charge stored by the second capacitor.

24. The apparatus of claim 23 , wherein the memory cell is a ferroelectric memory cell.

25. The apparatus of claim 23 , wherein:

the data state of the memory cell is a first data state if the comparison indicates the charge stored by the first capacitor is greater than the charge stored by the second capacitor; and

the data state of the memory cell is a second data state if the comparison indicates the charge stored by the first capacitor is less than the charge stored by the second capacitor.

26. The apparatus of claim 23 , wherein:

the first signal is applied to the first transistor while the first sensing voltage is being applied to the memory cell such that the first capacitor is coupled to the memory cell while the first sensing voltage is being applied to the memory cell; and

the second signal is applied to the second transistor while the second sensing voltage is being applied to the memory cell such that the second capacitor is coupled to the memory cell while the second sensing voltage is being applied to the memory cell.