Multi-phase clock division
View Patent ↗Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.
1. A semiconductor device comprising:
memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises:
count detection circuitry configured to count bits received for a phase of the plurality of phases; and
phase detection circuitry configured to identify which phase of the plurality of phases received a pulse of the data strobe first.
2. The semiconductor device of claim 1 , wherein the plurality of phases comprises four phases.
3. The semiconductor device of claim 2 , wherein:
a first phase of the plurality of phases corresponds to rising edges of a first set of pulses of the data strobe;
a second phase of the plurality of phases corresponds to falling edges of the first set of pulses of the data strobe;
a third phase of the plurality of phases corresponds to rising edges of a second set of pulses of the data strobe, wherein each pulse of the second set of pulses occurs between two pulses of the first set of pulses; and
a fourth phase of the plurality of phases corresponds to falling edges of the second set of pulses of the data strobe.
4. The semiconductor device of claim 1 , comprising a toggle flip-flop that is configured to:
receive the data strobe; and
toggle between a first mode and a second mode with each pulse of the data strobe, wherein the first mode directs an output of the toggle flip-flop to a first channel, and the second mode directs the output to a second channel.
5. The semiconductor device of claim 4 , wherein the first channel comprises:
a first rising edge flip-flop that receives the output and uses the data strobe to output every other rising edge of the data strobe; and
a second rising edge flip-flop that receives the output and uses the data strobe to output alternative rising edges between the every other rising edge of the data strobe.
6. The semiconductor device of claim 5 , wherein the second channel comprises:
a first falling edge flip-flop that receives the output and uses the data strobe to output every other falling edge of the data strobe; and
a second falling edge flip-flop that receives the output and uses the data strobe to output alternative falling edges between the every other falling edges of the data strobe.
7. The semiconductor device of claim 6 , wherein using the data strobe to output every other falling edge and alternative falling edges comprises using a data strobe false that is an inversion of the data strobe.
8. The semiconductor device of claim 6 , wherein the second channel comprises a latch to track falling edges of the data strobe.
9. The semiconductor device of claim 1 , comprising an amplifier that changes power of the data strobe from an external level to an internal level.
10. A semiconductor device comprising:
memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive a data strobe to assist in writing the data to the memory; and
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises count detection circuitry configured to count bits received for a phase of the plurality of phases.
11. The semiconductor device of claim 10 , wherein the count detection circuitry counts bits for less than all of the plurality of phases.
12. The semiconductor device of claim 10 , wherein the phase division circuitry comprises a channel for each phase of the plurality of phases, and wherein half of the channels include count detection circuitry.
13. The semiconductor device of claim 12 , wherein the half of the channels that include count detection circuitry correspond to rising edges of the data strobe.
14. The semiconductor device of claim 12 , wherein the half of the channels that include count detection circuitry correspond to falling edges of the data strobe.
15. The semiconductor device of claim 10 , wherein the count detection circuitry comprises a flip-flop that is configured to:
receive a write start as an input to the flip-flop;
receive the data strobe as a clock for the flip-flop; and
output a first count signal that indicates that a write command has begun being captured by the data strobe.
16. The semiconductor device of claim 15 , wherein the flip-flop is configured to receive a reset signal to reset a state of the flip-flop to an initial state.
17. A semiconductor device comprising:
memory;
a command interface configured to receive a write command to write data to the memory;
a data strobe pin configured to receive an external data strobe from a host device coupled to the semiconductor device, wherein the external data strobe is configured to assist in writing the data to the memory;
phase division circuitry configured to divide the data strobe into a plurality of phases to be used in writing the data to the memory, wherein the phase division circuitry comprises:
count detection circuitry configured to count bits received for a phase of the plurality of phases; and
phase detection circuitry configured to identify which phase of the plurality of phases received a pulse of the data strobe first.
18. The semiconductor device of claim 17 , wherein the phase division circuitry comprises a channel for each phase of the plurality of phases, and the phase detection circuitry is configured to determine whether a first channel or a second channel have begun counting bits first.
19. The semiconductor device of claim 18 , wherein the first channel and second channel correspond to phases of the plurality of phases having an edge-type, and the edge-type comprises rising edges or falling edges of the data strobe.
20. The semiconductor device of claim 18 , wherein the count detection circuitry comprises:
delay circuitry configured to delay bit counting in a delayed bit counting route;
a bypass output that bypasses the delay circuitry in a delay-bypassed route;
selection circuitry configured to output a signal indicating whether to use the delay circuitry based at least in part on whether a write preamble for the write command is longer than a threshold value; and
a selector that selects between the delay-bypassed route and the delayed bit counting route based on the signal.
21. The semiconductor device of claim 20 , wherein the selector comprises a multiplexor that uses the signal to select between the delay-bypassed route and the delayed bit counting route.
22. The semiconductor device of claim 20 , wherein the selection circuitry is configured to output the signal based at least in part on whether the second channel is currently capturing a write command when the selection circuitry is in the first channel.