Systems having a resistive memory device

1. A system comprising:

a controller configured to control the system; and

a resistive memory device coupled to the controller, the memory device comprising:

an array of resistive memory cells organized in rows and columns wherein each column of memory cells is coupled to a data line and each row of memory cells is coupled to an access line;

sense circuitry coupled to the access lines and configured to read data stored in the array of resistive memory cells;

row decoders coupled to the data lines and configured to bias a selected data line with programming pulses during a programming operation; and

control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells coupled to the selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data bits wherein the pairs of adjacent memory cells comprise memory cells that have a back-to-back relationship.

2. The system of claim 1 wherein each memory cell comprises a resistive storage element and a select device.

3. The system of claim 2 wherein the select device comprises one of: a MOSFET, a bipolar junction transistor, or a diode.

4. The system of claim 2 wherein the select device is one of: a two terminal device or a three terminal device.

5. The system of claim 1 wherein the memory cells having the back-to-back relationship share a SiN material.

6. The system of claim 1 , wherein the memory cells that have a back-to-back relationship comprises memory cells separated by a first distance along an axis in a direction of the selected data line, and wherein a particular memory cell of the memory cells that have the back-to-back relationship is separated from an adjacent memory cell by a second distance, greater than the first distance, along the axis.

7. The system of claim 1 , wherein the array of memory cells comprises a plurality of memory cells, wherein each memory cell of the plurality of memory cells comprises:

a respective resistive storage element of a plurality of resistive storage elements in a shared resistance variable material; and

a respective select device of a plurality of select devices coupled to its respective resistive storage element.

8. The system of claim 7 , wherein the respective resistive storage element of a memory cell of the plurality of memory cells and the respective select device of that memory cell of the plurality of memory cells are coupled in series.

9. The system of claim 7 , wherein each memory cell of the plurality of memory cells further comprises a respective heater coupled in series with its respective resistive storage element and its respective select device.

10. The system of claim 9 , further comprising:

wherein the respective heater of a first memory cell of the plurality of memory cells and the respective heater of a second memory cell of the plurality of memory cells having the back-to-back relationship are separated by a first dielectric material; and

wherein the respective heater of the first memory cell is separated from the respective heater of a different memory cell not having the back-to-back relationship by a second dielectric material different from the first dielectric material.

11. The system of claim 10 , wherein the respective heater of the first memory cell is further separated from the respective heater of the different memory cell by instances of the first dielectric material on opposing sides of the second dielectric material.

12. A system comprising:

a controller configured to control the system; and

a resistive memory device coupled to the controller, the memory device comprising:

an array of resistive memory cells comprising a plurality of resistive memory cells organized in rows and columns wherein each column of memory cells is coupled to a corresponding data line of a plurality of data lines and each row of memory cells is coupled to a corresponding access line of a plurality of access lines;

sense circuitry coupled to the access lines of the plurality of access lines and configured to read data stored in the array of resistive memory cells;

row decoders coupled to the data lines of the plurality of data lines and configured to bias a selected data line with programming pulses during a programming operation; and

control circuitry configured to build a data word from remapped data bits from a received data word such that pairs of data bits that are both to be programmed are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells of the plurality of resistive memory cells coupled to the selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data bits wherein the pairs of adjacent memory cells comprise memory cells that have a back-to-back relationship separated by a first distance along an axis in a direction of the selected data line.

13. The method of claim 12 , wherein building the data word comprises changing a bit order of the received data word.

14. The method of claim 13 , wherein changing the bit order of the received data word comprises moving a bit of data of the received data word that is to be programmed to a bit location of the received data word containing a bit of data that is not to be programmed.

15. The method of claim 12 , wherein building the data word comprises moving a bit of data of the received data word to a bit location of the built data word different than its bit location in the received data word.

16. The method of claim 15 , wherein moving the bit of the data word to the bit location of the built data word different than its bit location in the received data word comprises moving a bit of data of the received data word that is to be programmed, and wherein the bit location of the built data word corresponds to a bit of data of the received data word that is not to be programmed.

17. The method of claim 12 , wherein programming the built data word to memory cells of the plurality of resistive memory cells comprises changing a resistance of a resistance variable material for each memory cell of the plurality of resistive memory cells to be programmed.

18. The method of claim 12 , wherein programming the built data word to memory cells of the plurality of resistive memory cells comprises enabling a respective heater for each memory cell of the plurality of resistive memory cells to be programmed.

19. A system comprising:

a controller configured to control the system; and

a resistive memory device coupled to the controller, the memory device comprising:

an array of resistive memory cells comprising a plurality of resistive memory cells organized in rows and columns wherein each column of memory cells is coupled to a corresponding data line of a plurality of data lines and each row of memory cells is coupled to a corresponding access line of a plurality of access lines;

sense circuitry coupled to the access lines of the plurality of access lines and configured to read data stored in the array of resistive memory cells;

row decoders coupled to the data lines of the plurality of data lines and configured to bias a selected data line with programming pulses during a programming operation; and

control circuitry configured to build a data word from remapped data bits from a received data word by changing a bit order of the received data word such that pairs of data bits that are both to be programmed are mapped to adjacent locations in the built data word, the control circuitry further configured to program the built data word to memory cells of the plurality of resistive memory cells coupled to the selected data line such that, during a same program operation, pairs of adjacent memory cells along the selected data line are programmed with the pairs of data bits wherein the pairs of adjacent memory cells comprise memory cells that have a back-to-back relationship separated by a first distance along an axis in a direction of the selected data line;

wherein programming the built data word to memory cells of the plurality of resistive memory cells comprises changing a resistance of a resistance variable material for each memory cell of the plurality of resistive memory cells to be programmed.

20. The method of claim 19 , wherein changing the bit order of the received data word comprises moving a bit of data of the received data word that is to be programmed to a bit location of the received data word containing a bit of data that is not to be programmed.